269 lines
6.6 KiB
C
269 lines
6.6 KiB
C
/*
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* Copyright (c) 2019 Gerson Fernando Budke
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* Copyright (c) 2016 Piotr Mienkowski
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* SPDX-License-Identifier: Apache-2.0
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*/
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/** @file
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* @brief Atmel SAM V71 MCU initialization code
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*
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* This file provides routines to initialize and support board-level hardware
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* for the Atmel SAM V71 MCU.
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*/
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#include <kernel.h>
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#include <device.h>
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#include <init.h>
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#include <soc.h>
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#include <arch/arm/aarch32/cortex_m/cmsis.h>
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#include <logging/log.h>
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#define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
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LOG_MODULE_REGISTER(soc);
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/* Power Manager Controller */
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/*
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* PLL clock = Main * (MULA + 1) / DIVA
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*
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* By default, MULA == 24, DIVA == 1.
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* With main crystal running at 12 MHz,
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* PLL = 12 * (24 + 1) / 1 = 300 MHz
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*
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* With Processor Clock prescaler at 1
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* Processor Clock (HCLK)=300 MHz.
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*/
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#define PMC_CKGR_PLLAR_MULA \
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(CKGR_PLLAR_MULA(CONFIG_SOC_ATMEL_SAMV71_PLLA_MULA))
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#define PMC_CKGR_PLLAR_DIVA \
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(CKGR_PLLAR_DIVA(CONFIG_SOC_ATMEL_SAMV71_PLLA_DIVA))
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#if CONFIG_SOC_ATMEL_SAMV71_MDIV == 1
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#define SOC_ATMEL_SAMV71_MDIV PMC_MCKR_MDIV_EQ_PCK
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#elif CONFIG_SOC_ATMEL_SAMV71_MDIV == 2
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#define SOC_ATMEL_SAMV71_MDIV PMC_MCKR_MDIV_PCK_DIV2
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#elif CONFIG_SOC_ATMEL_SAMV71_MDIV == 3
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#define SOC_ATMEL_SAMV71_MDIV PMC_MCKR_MDIV_PCK_DIV3
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#elif CONFIG_SOC_ATMEL_SAMV71_MDIV == 4
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#define SOC_ATMEL_SAMV71_MDIV PMC_MCKR_MDIV_PCK_DIV4
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#else
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#error "Invalid CONFIG_SOC_ATMEL_SAMV71_MDIV define value"
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#endif
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/**
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* @brief Setup various clocks on SoC at boot time.
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*
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* Setup Slow, Main, PLLA, Processor and Master clocks during the device boot.
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* It is assumed that the relevant registers are at their reset value.
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*/
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static ALWAYS_INLINE void clock_init(void)
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{
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uint32_t reg_val;
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#ifdef CONFIG_SOC_ATMEL_SAMV71_EXT_SLCK
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/* Switch slow clock to the external 32 kHz crystal oscillator */
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SUPC->SUPC_CR = SUPC_CR_KEY_PASSWD | SUPC_CR_XTALSEL;
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/* Wait for oscillator to be stabilized */
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while (!(SUPC->SUPC_SR & SUPC_SR_OSCSEL)) {
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;
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}
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#endif /* CONFIG_SOC_ATMEL_SAMV71_EXT_SLCK */
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#ifdef CONFIG_SOC_ATMEL_SAMV71_EXT_MAINCK
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/*
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* Setup main external crystal oscillator if not already done
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* by a previous program i.e. bootloader
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*/
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if (!(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL_Msk)) {
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/* Start the external crystal oscillator */
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PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD
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/* We select maximum setup time.
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* While start up time could be shortened
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* this optimization is not deemed
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* critical now.
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*/
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| CKGR_MOR_MOSCXTST(0xFFu)
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/* RC OSC must stay on */
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| CKGR_MOR_MOSCRCEN
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| CKGR_MOR_MOSCXTEN;
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/* Wait for oscillator to be stabilized */
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while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)) {
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;
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}
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/* Select the external crystal oscillator as main clock */
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PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD
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| CKGR_MOR_MOSCSEL
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| CKGR_MOR_MOSCXTST(0xFFu)
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| CKGR_MOR_MOSCRCEN
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| CKGR_MOR_MOSCXTEN;
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/* Wait for external oscillator to be selected */
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while (!(PMC->PMC_SR & PMC_SR_MOSCSELS)) {
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;
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}
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}
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/* Turn off RC OSC, not used any longer, to save power */
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PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD
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| CKGR_MOR_MOSCSEL
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| CKGR_MOR_MOSCXTST(0xFFu)
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| CKGR_MOR_MOSCXTEN;
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/* Wait for RC OSC to be turned off */
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while (PMC->PMC_SR & PMC_SR_MOSCRCS) {
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;
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}
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#ifdef CONFIG_SOC_ATMEL_SAMV71_WAIT_MODE
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/*
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* Instruct CPU to enter Wait mode instead of Sleep mode to
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* keep Processor Clock (HCLK) and thus be able to debug
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* CPU using JTAG
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*/
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PMC->PMC_FSMR |= PMC_FSMR_LPM;
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#endif
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#else
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/* Attempt to change main fast RC oscillator frequency */
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/*
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* NOTE: MOSCRCF must be changed only if MOSCRCS is set in the PMC_SR
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* register, should normally be the case here
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*/
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while (!(PMC->PMC_SR & PMC_SR_MOSCRCS)) {
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;
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}
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/* Set main fast RC oscillator to 12 MHz */
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PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD
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| CKGR_MOR_MOSCRCF_12_MHz
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| CKGR_MOR_MOSCRCEN;
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/* Wait for oscillator to be stabilized */
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while (!(PMC->PMC_SR & PMC_SR_MOSCRCS)) {
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;
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}
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#endif /* CONFIG_SOC_ATMEL_SAMV71_EXT_MAINCK */
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/*
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* Setup PLLA
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*/
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/* Switch MCK (Master Clock) to the main clock first */
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reg_val = PMC->PMC_MCKR & ~PMC_MCKR_CSS_Msk;
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PMC->PMC_MCKR = reg_val | PMC_MCKR_CSS_MAIN_CLK;
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/* Wait for clock selection to complete */
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while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
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;
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}
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/* Setup PLLA */
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PMC->CKGR_PLLAR = CKGR_PLLAR_ONE
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| PMC_CKGR_PLLAR_MULA
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| CKGR_PLLAR_PLLACOUNT(0x3Fu)
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| PMC_CKGR_PLLAR_DIVA;
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/*
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* NOTE: Both MULA and DIVA must be set to a value greater than 0 or
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* otherwise PLL will be disabled. In this case we would get stuck in
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* the following loop.
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*/
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/* Wait for PLL lock */
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while (!(PMC->PMC_SR & PMC_SR_LOCKA)) {
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;
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}
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/*
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* Final setup of the Master Clock
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*/
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/*
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* NOTE: PMC_MCKR must not be programmed in a single write operation.
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* If CSS, MDIV or PRES are modified we must wait for MCKRDY bit to be
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* set again.
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*/
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/* Setup prescaler - PLLA Clock / Processor Clock (HCLK) */
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reg_val = PMC->PMC_MCKR & ~PMC_MCKR_PRES_Msk;
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PMC->PMC_MCKR = reg_val | PMC_MCKR_PRES_CLK_1;
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/* Wait for Master Clock setup to complete */
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while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
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;
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}
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/* Setup divider - Processor Clock (HCLK) / Master Clock (MCK) */
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reg_val = PMC->PMC_MCKR & ~PMC_MCKR_MDIV_Msk;
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PMC->PMC_MCKR = reg_val | SOC_ATMEL_SAMV71_MDIV;
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/* Wait for Master Clock setup to complete */
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while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
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;
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}
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/* Finally select PLL as Master Clock source */
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reg_val = PMC->PMC_MCKR & ~PMC_MCKR_CSS_Msk;
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PMC->PMC_MCKR = reg_val | PMC_MCKR_CSS_PLLA_CLK;
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/* Wait for Master Clock setup to complete */
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while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
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;
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}
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}
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/**
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* @brief Perform basic hardware initialization at boot.
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*
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* This needs to be run at the very beginning.
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* So the init priority has to be 0 (zero).
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*
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* @return 0
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*/
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static int atmel_samv71_init(const struct device *arg)
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{
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uint32_t key;
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ARG_UNUSED(arg);
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key = irq_lock();
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SCB_EnableICache();
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if (!(SCB->CCR & SCB_CCR_DC_Msk)) {
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SCB_EnableDCache();
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}
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/*
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* Set FWS (Flash Wait State) value before increasing Master Clock
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* (MCK) frequency.
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* TODO: set FWS based on the actual MCK frequency and VDDIO value
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* rather than maximum supported 150 MHz at standard VDDIO=2.7V
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*/
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EFC->EEFC_FMR = EEFC_FMR_FWS(5) | EEFC_FMR_CLOE;
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/* Setup system clocks */
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clock_init();
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/* Install default handler that simply resets the CPU
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* if configured in the kernel, NOP otherwise
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*/
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NMI_INIT();
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irq_unlock(key);
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/* Check that the CHIP CIDR matches the HAL one */
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if (CHIPID->CHIPID_CIDR != CHIP_CIDR) {
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LOG_WRN("CIDR mismatch: chip = 0x%08x vs HAL = 0x%08x",
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(uint32_t)CHIPID->CHIPID_CIDR, (uint32_t)CHIP_CIDR);
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}
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return 0;
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}
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SYS_INIT(atmel_samv71_init, PRE_KERNEL_1, 0);
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