Adithya Baglody 1d27b404a6 tests: benchmarks: timing_info: Enable benchmarks for riscv32. ... This patch provides support needed to get timing related information from riscv32 based SOC. Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>		2018-08-20 06:51:25 -07:00
..
CMakeLists.txt	…
gen_isr_tables.py	gen_isr_tables: Delete the dead code accompanying .intList.num_isrs	2018-06-25 12:54:49 -07:00
isr_tables.c	gen_isr_tables: Delete the dead code accompanying .intList.num_isrs	2018-06-25 12:54:49 -07:00
timing_info_bench.c	tests: benchmarks: timing_info: Enable benchmarks for riscv32.	2018-08-20 06:51:25 -07:00