90 lines
1.7 KiB
C
90 lines
1.7 KiB
C
/*
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* Copyright (c) 2016 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief System/hardware module for Nordic Semiconductor nRF52 family processor
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*
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* This module provides routines to initialize and support board-level hardware
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* for the Nordic Semiconductor nRF52 family processor.
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*/
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#include <kernel.h>
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#include <init.h>
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#include <cortex_m/exc.h>
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#include <nrfx.h>
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#include <nrf_power.h>
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#include <soc/nrfx_coredep.h>
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#include <logging/log.h>
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#ifdef CONFIG_RUNTIME_NMI
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extern void _NmiInit(void);
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#define NMI_INIT() _NmiInit()
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#else
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#define NMI_INIT()
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#endif
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#if defined(CONFIG_SOC_NRF52810)
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#include <system_nrf52810.h>
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#elif defined(CONFIG_SOC_NRF52832)
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#include <system_nrf52.h>
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#elif defined(CONFIG_SOC_NRF52840)
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#include <system_nrf52840.h>
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#else
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#error "Unknown SoC."
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#endif
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#include <hal/nrf_power.h>
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#define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
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LOG_MODULE_REGISTER(soc);
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/* Overrides the weak ARM implementation:
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Set general purpose retention register and reboot */
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void sys_arch_reboot(int type)
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{
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nrf_power_gpregret_set((uint8_t)type);
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NVIC_SystemReset();
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}
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static int nordicsemi_nrf52_init(struct device *arg)
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{
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u32_t key;
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ARG_UNUSED(arg);
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key = irq_lock();
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SystemInit();
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#ifdef CONFIG_NRF_ENABLE_ICACHE
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/* Enable the instruction cache */
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NRF_NVMC->ICACHECNF = NVMC_ICACHECNF_CACHEEN_Msk;
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#endif
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#if defined(CONFIG_SOC_DCDC_NRF52X)
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nrf_power_dcdcen_set(true);
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#endif
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_ClearFaults();
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/* Install default handler that simply resets the CPU
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* if configured in the kernel, NOP otherwise
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*/
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NMI_INIT();
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irq_unlock(key);
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return 0;
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}
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void z_arch_busy_wait(u32_t time_us)
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{
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nrfx_coredep_delay_us(time_us);
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}
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SYS_INIT(nordicsemi_nrf52_init, PRE_KERNEL_1, 0);
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