286 lines
6.6 KiB
Plaintext
286 lines
6.6 KiB
Plaintext
/*
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* Copyright (c) 2018, NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv7-m.dtsi>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/rdc/imx_rdc.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0>;
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status = "disabled";
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-m4f";
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reg = <0>;
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};
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};
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tcml:memory@1fff8000 {
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compatible = "nxp,imx-itcm";
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reg = <0x1fff8000 0x00008000>;
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label = "TCML";
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};
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tcmu:memory@20000000 {
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compatible = "nxp,imx-dtcm";
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reg = <0x20000000 0x00008000>;
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label = "TCMU";
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};
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ocram_s:memory@208f8000 {
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device_type = "memory";
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compatible = "nxp,imx-sys-bus";
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reg = <0x208f8000 0x00004000>;
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label = "OCRAM_S";
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};
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ocram:memory@20900000 {
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device_type = "memory";
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compatible = "nxp,imx-sys-bus";
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reg = <0x20900000 0x00020000>;
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label = "OCRAM";
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};
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ddr:memory@80000000 {
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device_type = "memory";
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compatible = "nxp,imx-sys-bus";
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reg = <0x80000000 0x60000000>;
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label = "DDR";
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};
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flash:memory@DT_FLASH_ADDR {
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compatible = "soc-nv-flash";
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reg = <DT_FLASH_ADDR DT_FLASH_SIZE>;
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};
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sram:memory@DT_SRAM_ADDR {
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reg = <DT_SRAM_ADDR DT_SRAM_SIZE>;
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};
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soc {
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uart1:uart@42020000 {
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compatible = "nxp,imx-uart";
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reg = <0x42020000 0x00004000>;
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interrupts = <26 0>;
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rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW)|\
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RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW))>;
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label = "UART_1";
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status = "disabled";
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};
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uart2:uart@421e8000 {
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compatible = "nxp,imx-uart";
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reg = <0x421e8000 0x00004000>;
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interrupts = <27 0>;
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rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW)|\
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RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW))>;
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label = "UART_2";
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status = "disabled";
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};
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uart3:uart@421ec000 {
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compatible = "nxp,imx-uart";
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reg = <0x421ec000 0x00004000>;
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interrupts = <28 0>;
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rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW)|\
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RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW))>;
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label = "UART_3";
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status = "disabled";
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};
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uart4:uart@421f0000 {
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compatible = "nxp,imx-uart";
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reg = <0x421f0000 0x00004000>;
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interrupts = <29 0>;
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rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW)|\
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RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW))>;
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label = "UART_4";
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status = "disabled";
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};
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uart5:uart@421f4000 {
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compatible = "nxp,imx-uart";
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reg = <0x421f4000 0x00004000>;
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interrupts = <30 0>;
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rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW)|\
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RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW))>;
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label = "UART_5";
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status = "disabled";
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};
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uart6:uart@422a0000 {
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compatible = "nxp,imx-uart";
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reg = <0x422a0000 0x00004000>;
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interrupts = <17 0>;
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rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW)|\
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RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW))>;
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label = "UART_6";
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status = "disabled";
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};
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gpio1:gpio@4209c000 {
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compatible = "nxp,imx-gpio";
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reg = <0x4209c000 0x4000>;
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interrupts = <66 0>, <67 0>;
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rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW)|\
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RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW))>;
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label = "GPIO_1";
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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gpio2:gpio@420a0000 {
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compatible = "nxp,imx-gpio";
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reg = <0x420a0000 0x4000>;
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interrupts = <68 0>, <69 0>;
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rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW)|\
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RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW))>;
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label = "GPIO_2";
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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gpio3:gpio@420a4000 {
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compatible = "nxp,imx-gpio";
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reg = <0x420a4000 0x4000>;
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interrupts = <70 0>, <71 0>;
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rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW)|\
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RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW))>;
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label = "GPIO_3";
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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gpio4:gpio@420a8000 {
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compatible = "nxp,imx-gpio";
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reg = <0x420a8000 0x4000>;
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interrupts = <72 0>, <73 0>;
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rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW)|\
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RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW))>;
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label = "GPIO_4";
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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gpio5:gpio@420ac000 {
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compatible = "nxp,imx-gpio";
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reg = <0x420ac000 0x4000>;
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interrupts = <74 0>, <74 0>;
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rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW)|\
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RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW))>;
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label = "GPIO_5";
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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gpio6:gpio@420b0000 {
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compatible = "nxp,imx-gpio";
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reg = <0x420b0000 0x4000>;
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interrupts = <76 0>, <77 0>;
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rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW)|\
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RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW))>;
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label = "GPIO_6";
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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gpio7:gpio@420b4000 {
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compatible = "nxp,imx-gpio";
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reg = <0x420b4000 0x4000>;
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interrupts = <78 0>, <79 0>;
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rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW)|\
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RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW))>;
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label = "GPIO_7";
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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mub:mu@4229c000 {
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compatible = "nxp,imx-mu";
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reg = <0x4229c000 0x4000>;
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interrupts = <99 0>;
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rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW)|\
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RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW))>;
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label = "MU_B";
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status = "disabled";
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};
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epit1:epit@420d0000 {
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compatible = "nxp,imx-epit";
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reg = <0x420d0000 0x4000>;
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interrupts = <56 0>;
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prescaler = <0>;
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rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW)|\
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RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW))>;
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label = "EPIT_1";
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status = "disabled";
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};
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epit2:epit@420d4000 {
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compatible = "nxp,imx-epit";
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reg = <0x420d4000 0x4000>;
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interrupts = <57 0>;
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prescaler = <0>;
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rdc = <(RDC_DOMAIN_PERM(A9_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW)|\
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RDC_DOMAIN_PERM(M4_DOMAIN_ID,\
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RDC_DOMAIN_PERM_RW))>;
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label = "EPIT_2";
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status = "disabled";
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <4>;
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};
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