201 lines
4.1 KiB
Plaintext
201 lines
4.1 KiB
Plaintext
/*
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* Copyright (c) 2017, NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <dt-bindings/clock/mcux_lpc_syscon_clock.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/i2c/i2c.h>
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#include <mem.h>
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/ {
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aliases{
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gpio-0 = &gpio0;
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gpio-1 = &gpio1;
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mailbox-0 = &mailbox0;
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};
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chosen {
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zephyr,flash-controller = &iap;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-m4f";
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reg = <0>;
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};
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cpu1: cpu@1 {
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compatible = "arm,cortex-m0+";
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reg = <1>;
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};
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};
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soc {
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syscon: syscon@40000000 {
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compatible = "nxp,lpc-syscon";
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reg = <0x40000000 0x4000>;
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label = "SYSCON";
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#clock-cells = <1>;
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};
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sram0:memory@20000000 {
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compatible = "mmio-sram";
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reg = <0x20000000 DT_SIZE_K(64)>;
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};
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sram1:memory@20010000 {
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compatible = "mmio-sram";
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reg = <0x20010000 DT_SIZE_K(64)>;
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};
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sram2:memory@20020000 {
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compatible = "mmio-sram";
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reg = <0x20020000 DT_SIZE_K(32)>;
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};
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sramx:memory@4000000{
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compatible = "mmio-sram";
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reg = <0x4000000 DT_SIZE_K(32)>;
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};
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iap: flash-controller@4009c000 {
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compatible = "nxp,lpc-iap";
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label = "FLASH_IAP";
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reg = <0x4009c000 0x18>;
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#address-cells = <1>;
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#size-cells = <1>;
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flash0: flash@0 {
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compatible = "soc-nv-flash";
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reg = <0 DT_SIZE_K(256)>;
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label = "LPC_FLASH";
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erase-block-size = <256>;
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write-block-size = <256>;
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};
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};
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iocon: iocon@40001000 {
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compatible = "nxp,lpc-iocon";
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reg = <0x40001000 0x100>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x40001000 0x100>;
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pio0: pio0@0 {
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compatible = "nxp,lpc-iocon-pio";
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reg = <0x0 0x80>;
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};
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pio1: pio0@80 {
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compatible = "nxp,lpc-iocon-pio";
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reg = <0x80 0x80>;
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};
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};
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gpio0: gpio@0 {
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compatible = "nxp,lpc-gpio";
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reg = <0x4008c000 0x2488>;
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interrupts = <4 2>,<5 2>,<6 2>,<7 2>;
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label = "GPIO_0";
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpio1: gpio@1 {
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compatible = "nxp,lpc-gpio";
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reg = <0x4008C000 0x2488>;
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interrupts = <32 2>,<33 2>,<34 2>,<35 2>;
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label = "GPIO_1";
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gpio-controller;
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#gpio-cells = <2>;
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};
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mailbox0:mailbox@4008b000 {
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compatible = "nxp,lpc-mailbox";
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reg = <0x4008b000 0xEC>;
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interrupts = <31 0>;
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label = "MAILBOX_0";
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status = "disabled";
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};
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flexcomm0: flexcomm@40086000 {
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compatible = "nxp,lpc-flexcomm";
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reg = <0x40086000 0x1000>;
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interrupts = <14 0>;
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clocks = <&syscon MCUX_FLEXCOMM0_CLK>;
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label = "FLEXCOMM_0";
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status = "disabled";
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};
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flexcomm1: flexcomm@40087000 {
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compatible = "nxp,lpc-flexcomm";
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reg = <0x40087000 0x1000>;
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interrupts = <15 0>;
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clocks = <&syscon MCUX_FLEXCOMM1_CLK>;
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label = "FLEXCOMM_1";
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status = "disabled";
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};
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flexcomm2: flexcomm@40088000 {
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compatible = "nxp,lpc-flexcomm";
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reg = <0x40088000 0x1000>;
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interrupts = <16 0>;
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clocks = <&syscon MCUX_FLEXCOMM2_CLK>;
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label = "FLEXCOMM_2";
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status = "disabled";
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};
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flexcomm3: flexcomm@40089000 {
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compatible = "nxp,lpc-flexcomm";
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reg = <0x40089000 0x1000>;
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interrupts = <17 0>;
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clocks = <&syscon MCUX_FLEXCOMM3_CLK>;
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label = "FLEXCOMM_3";
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status = "disabled";
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};
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flexcomm4: flexcomm@4008a000 {
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compatible = "nxp,lpc-flexcomm";
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reg = <0x4008a000 0x1000>;
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interrupts = <18 0>;
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clocks = <&syscon MCUX_FLEXCOMM4_CLK>;
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label = "FLEXCOMM_4";
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status = "disabled";
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};
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flexcomm5: flexcomm@40096000 {
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compatible = "nxp,lpc-flexcomm";
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reg = <0x40096000 0x1000>;
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interrupts = <19 0>;
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clocks = <&syscon MCUX_FLEXCOMM5_CLK>;
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label = "FLEXCOMM_5";
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status = "disabled";
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};
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flexcomm6: flexcomm@40097000 {
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compatible = "nxp,lpc-flexcomm";
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reg = <0x40097000 0x1000>;
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interrupts = <20 0>;
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clocks = <&syscon MCUX_FLEXCOMM6_CLK>;
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label = "FLEXCOMM_6";
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status = "disabled";
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};
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flexcomm7: flexcomm@40098000 {
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compatible = "nxp,lpc-flexcomm";
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reg = <0x40098000 0x1000>;
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interrupts = <21 0>;
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clocks = <&syscon MCUX_FLEXCOMM7_CLK>;
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label = "FLEXCOMM_7";
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status = "disabled";
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <3>;
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};
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