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zephyr/dts/arm/nxp/nxp_k6x.dtsi

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/* SPDX-License-Identifier: Apache-2.0 */
#include <mem.h>
#include <arm/armv7-m.dtsi>
#include <dt-bindings/clock/kinetis_sim.h>
#include <dt-bindings/clock/kinetis_mcg.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/i2c/i2c.h>
/ {
aliases {
watchdog0 = &wdog;
};
chosen {
zephyr,entropy = &rnga;
zephyr,flash-controller = &ftfe;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m4f";
reg = <0>;
};
};
/* The on-chip SRAM is split into SRAM_L and SRAM_U regions that form a
* contiguous block in the memory map, however misaligned accesses
* across the 0x2000_0000 boundary are not supported in the Arm
* Cortex-M4 architecture. For clarity and to avoid the temptation for
* someone to extend sram0 without solving this issue, we define two
* separate memory nodes here and only use the upper one for now. A
* potential solution has been proposed in binutils:
* https://sourceware.org/ml/binutils/2017-02/msg00250.html
*/
sram_l: memory@1fff0000 {
compatible = "mmio-sram";
reg = <0x1fff0000 DT_SIZE_K(64)>;
};
sram0: memory@20000000 {
compatible = "mmio-sram";
reg = <0x20000000 DT_SIZE_K(192)>;
};
temp0: temp0 {
compatible = "nxp,kinetis-temperature";
io-channels = <&adc0 26>, <&adc0 27>;
io-channel-names = "SENSOR", "BANDGAP";
bandgap-voltage = <1000000>;
vtemp25 = <716000>;
sensor-slope-cold = <1620>;
sensor-slope-hot = <1620>;
label = "TEMP0";
status = "disabled";
};
temp1: temp1 {
compatible = "nxp,kinetis-temperature";
io-channels = <&adc1 26>, <&adc1 27>;
io-channel-names = "SENSOR", "BANDGAP";
bandgap-voltage = <1000000>;
vtemp25 = <716000>;
sensor-slope-cold = <1620>;
sensor-slope-hot = <1620>;
label = "TEMP1";
status = "disabled";
};
soc {
mpu: mpu@4000d000 {
compatible = "nxp,k64f-mpu";
reg = <0x4000d000 0x824>;
status = "disabled";
};
mcg: clock-controller@40064000 {
compatible = "nxp,kinetis-mcg";
reg = <0x40064000 0xd>;
label = "MCG";
#clock-cells = <1>;
};
osc: clock-controller@40065000 {
compatible = "nxp,k64f-osc";
reg = <0x40065000 0x4>;
enable-external-reference;
};
rtc: rtc@4003d000 {
compatible = "nxp,kinetis-rtc";
reg = <0x4003d000 0x1000>;
interrupts = <46 0>, <47 0>;
interrupt-names = "alarm", "seconds";
clock-frequency = <32768>;
prescaler = <32768>;
label = "RTC_0";
};
sim: sim@40047000 {
compatible = "nxp,kinetis-sim";
reg = <0x40047000 0x1060>;
label = "SIM";
#clock-cells = <3>;
core_clk {
compatible = "fixed-factor-clock";
clocks = <&mcg KINETIS_MCG_OUT_CLK>;
clock-div = <1>;
#clock-cells = <0>;
};
bus_clk {
compatible = "fixed-factor-clock";
clocks = <&mcg KINETIS_MCG_OUT_CLK>;
clock-div = <2>;
#clock-cells = <0>;
};
flexbus_clk {
compatible = "fixed-factor-clock";
clocks = <&mcg KINETIS_MCG_OUT_CLK>;
clock-div = <3>;
#clock-cells = <0>;
};
flash_clk {
compatible = "fixed-factor-clock";
clocks = <&mcg KINETIS_MCG_OUT_CLK>;
clock-div = <5>;
#clock-cells = <0>;
};
};
ftfe: flash-controller@40020000 {
compatible = "nxp,kinetis-ftfe";
label = "FLASH_CTRL";
reg = <0x40020000 0x18>;
interrupts = <18 0>, <19 0>;
interrupt-names = "command-complete", "read-collision";
#address-cells = <1>;
#size-cells = <1>;
flash0: flash@0 {
compatible = "soc-nv-flash";
label = "MCUX_FLASH";
reg = <0 DT_SIZE_M(1)>;
erase-block-size = <4096>;
write-block-size = <8>;
};
};
i2c0: i2c@40066000 {
compatible = "nxp,kinetis-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40066000 0x1000>;
interrupts = <24 0>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 6>;
label = "I2C_0";
status = "disabled";
};
i2c1: i2c@40067000 {
compatible = "nxp,kinetis-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40067000 0x1000>;
interrupts = <25 0>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 7>;
label = "I2C_1";
status = "disabled";
};
i2c2: i2c@400e6000 {
compatible = "nxp,kinetis-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x400e6000 0x1000>;
interrupts = <74 0>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1028 6>;
label = "I2C_2";
status = "disabled";
};
uart0: uart@4006a000 {
compatible = "nxp,kinetis-uart";
reg = <0x4006a000 0x1000>;
interrupts = <31 0>, <32 0>;
interrupt-names = "status", "error";
clocks = <&sim KINETIS_SIM_CORESYS_CLK 0x1034 10>;
label = "UART_0";
status = "disabled";
};
uart1: uart@4006b000 {
compatible = "nxp,kinetis-uart";
reg = <0x4006b000 0x1000>;
interrupts = <33 0>, <34 0>;
interrupt-names = "status", "error";
clocks = <&sim KINETIS_SIM_CORESYS_CLK 0x1034 11>;
label = "UART_1";
status = "disabled";
};
uart2: uart@4006c000 {
compatible = "nxp,kinetis-uart";
reg = <0x4006c000 0x1000>;
interrupts = <35 0>, <36 0>;
interrupt-names = "status", "error";
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 12>;
label = "UART_2";
status = "disabled";
};
uart3: uart@4006d000 {
compatible = "nxp,kinetis-uart";
reg = <0x4006d000 0x1000>;
interrupts = <37 0>, <38 0>;
interrupt-names = "status", "error";
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 13>;
label = "UART_3";
status = "disabled";
};
uart4: uart@400ea000 {
compatible = "nxp,kinetis-uart";
reg = <0x400ea000 0x1000>;
interrupts = <66 0>, <67 0>;
interrupt-names = "status", "error";
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1028 10>;
label = "UART_4";
status = "disabled";
};
uart5: uart@400eb000 {
compatible = "nxp,kinetis-uart";
reg = <0x400eb000 0x1000>;
interrupts = <68 0>, <69 0>;
interrupt-names = "status", "error";
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1028 11>;
label = "UART_5";
status = "disabled";
};
porta: pinmux@40049000 {
compatible = "nxp,kinetis-pinmux";
reg = <0x40049000 0xd0>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 9>;
};
portb: pinmux@4004a000 {
compatible = "nxp,kinetis-pinmux";
reg = <0x4004a000 0xd0>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 10>;
};
portc: pinmux@4004b000 {
compatible = "nxp,kinetis-pinmux";
reg = <0x4004b000 0xd0>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 11>;
};
portd: pinmux@4004c000 {
compatible = "nxp,kinetis-pinmux";
reg = <0x4004c000 0xd0>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 12>;
};
porte: pinmux@4004d000 {
compatible = "nxp,kinetis-pinmux";
reg = <0x4004d000 0xd0>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 13>;
};
gpioa: gpio@400ff000 {
compatible = "nxp,kinetis-gpio";
status = "disabled";
reg = <0x400ff000 0x40>;
interrupts = <59 2>;
label = "GPIO_0";
gpio-controller;
#gpio-cells = <2>;
nxp,kinetis-port = <&porta>;
};
gpiob: gpio@400ff040 {
compatible = "nxp,kinetis-gpio";
status = "disabled";
reg = <0x400ff040 0x40>;
interrupts = <60 2>;
label = "GPIO_1";
gpio-controller;
#gpio-cells = <2>;
nxp,kinetis-port = <&portb>;
};
gpioc: gpio@400ff080 {
compatible = "nxp,kinetis-gpio";
status = "disabled";
reg = <0x400ff080 0x40>;
interrupts = <61 2>;
label = "GPIO_2";
gpio-controller;
#gpio-cells = <2>;
nxp,kinetis-port = <&portc>;
};
gpiod: gpio@400ff0c0 {
compatible = "nxp,kinetis-gpio";
status = "disabled";
reg = <0x400ff0c0 0x40>;
interrupts = <62 2>;
label = "GPIO_3";
gpio-controller;
#gpio-cells = <2>;
nxp,kinetis-port = <&portd>;
};
gpioe: gpio@400ff100 {
compatible = "nxp,kinetis-gpio";
status = "disabled";
reg = <0x400ff100 0x40>;
interrupts = <63 2>;
label = "GPIO_4";
gpio-controller;
#gpio-cells = <2>;
nxp,kinetis-port = <&porte>;
};
spi0: spi@4002c000 {
compatible = "nxp,kinetis-dspi";
reg = <0x4002c000 0x88>;
interrupts = <26 3>;
label = "SPI_0";
clocks = <&sim KINETIS_SIM_BUS_CLK 0x103C 12>;
#address-cells = <1>;
#size-cells = <0>;
};
spi1: spi@4002d000 {
compatible = "nxp,kinetis-dspi";
reg = <0x4002d000 0x88>;
interrupts = <27 3>;
label = "SPI_1";
clocks = <&sim KINETIS_SIM_BUS_CLK 0x103C 13>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi2: spi@400ac000 {
compatible = "nxp,kinetis-dspi";
reg = <0x400ac000 0x88>;
interrupts = <65 3>;
label = "SPI_2";
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1030 12>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
wdog: watchdog@40052000 {
compatible = "nxp,kinetis-wdog";
reg = <0x40052000 16>;
interrupts = <22 0>;
clocks = <&sim KINETIS_SIM_LPO_CLK 0 0>;
label = "WDT_0";
};
ftm0: ftm@40038000{
compatible = "nxp,kinetis-ftm";
reg = <0x40038000 0x98>;
interrupts = <42 0>;
clocks = <&mcg KINETIS_MCG_FIXED_FREQ_CLK>;
prescaler = <16>;
label = "FTM_0";
status = "disabled";
};
ftm1: ftm@40039000{
compatible = "nxp,kinetis-ftm";
reg = <0x40039000 0x98>;
interrupts = <43 0>;
clocks = <&mcg KINETIS_MCG_FIXED_FREQ_CLK>;
prescaler = <16>;
label = "FTM_1";
status = "disabled";
};
ftm2: ftm@4003a000{
compatible = "nxp,kinetis-ftm";
reg = <0x4003a000 0x98>;
interrupts = <44 0>;
clocks = <&mcg KINETIS_MCG_FIXED_FREQ_CLK>;
prescaler = <16>;
label = "FTM_2";
status = "disabled";
};
ftm3: ftm@400b9000{
compatible = "nxp,kinetis-ftm";
reg = <0x400b9000 0x98>;
interrupts = <71 0>;
clocks = <&mcg KINETIS_MCG_FIXED_FREQ_CLK>;
prescaler = <16>;
label = "FTM_3";
status = "disabled";
};
adc0: adc@4003b000{
compatible = "nxp,kinetis-adc16";
reg = <0x4003b000 0x70>;
interrupts = <39 0>;
label = "ADC_0";
status = "disabled";
#io-channel-cells = <1>;
};
adc1: adc@400bb000{
compatible = "nxp,kinetis-adc16";
reg = <0x400bb000 0x70>;
interrupts = <73 0>;
label = "ADC_1";
status = "disabled";
#io-channel-cells = <1>;
};
dac0: dac@400cc000 {
compatible = "nxp,kinetis-dac";
reg = <0x400cc000 0x1000>;
interrupts = <56 0>;
voltage-reference = <1>;
label = "DAC_0";
status = "disabled";
#io-channel-cells = <1>;
};
dac1: dac@400cd000 {
compatible = "nxp,kinetis-dac";
reg = <0x400cd000 0x1000>;
interrupts = <72 0>;
voltage-reference = <1>;
label = "DAC_1";
status = "disabled";
#io-channel-cells = <1>;
};
usbotg: usbd@40072000 {
compatible = "nxp,kinetis-usbd";
reg = <0x40072000 0x1000>;
interrupts = <53 1>;
interrupt-names = "usb_otg";
num-bidir-endpoints = <16>;
status = "disabled";
label = "USBD";
};
enet: ethernet@400c0000 {
compatible = "nxp,kinetis-ethernet";
reg = <0x400c0000 0x620>;
interrupts = <83 0>, <84 0>, <85 0>;
interrupt-names = "TX", "RX", "ERR";
status = "disabled";
label = "ETH_0";
clocks = <&sim KINETIS_SIM_CORESYS_CLK 0 0>;
ptp {
compatible = "nxp,kinetis-ptp";
status = "disabled";
interrupts = <82 0>;
interrupt-names = "IEEE1588_TMR";
};
};
rnga: random@40029000 {
compatible = "nxp,kinetis-rnga";
reg = <0x40029000 0x1000>;
status = "okay";
interrupts = <23 0>;
label = "RNGA";
};
flexcan0: can@40024000 {
compatible = "nxp,kinetis-flexcan";
reg = <0x40024000 0x1000>;
interrupts = <75 0>, <76 0>, <77 0>, <78 0>, <79 0>, <80 0>;
interrupt-names = "mb-0-15", "bus-off", "error", "tx-warning", "rx-warning", "wake-up";
clocks = <&sim KINETIS_SIM_BUS_CLK 0x103C 4>;
clk-source = <1>;
label = "CAN_0";
sjw = <1>;
prop-seg = <1>;
phase-seg1 = <3>;
phase-seg2 = <2>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
edma0: dma-controller@40008000 {
#dma-cells = <2>;
compatible = "nxp,mcux-edma";
dma-channels = <16>;
dma-requests = <64>;
nxp,mem2mem;
reg = <0x40008000 0x1000>,
<0x40021000 0x1000>;
interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
<4 0>, <5 0>, <6 0>, <7 0>,
<8 0>, <9 0>, <10 0>, <11 0>,
<12 0>, <13 0>, <14 0>, <15 0>,
<16 0>;
clocks = <&sim KINETIS_SIM_DMA_CLK 0x1040 0x00000002>,
<&sim KINETIS_SIM_DMAMUX_CLK 0x103C 0x00000002>;
status = "disabled";
label = "DMA_0";
};
pit0: pit@40037000 {
compatible = "nxp,kinetis-pit";
reg = <0x40037000 0x1000>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x103c 23>;
interrupts = <48 0>, <49 0>, <50 0>, <51 0>;
status = "disabled";
pit-channel = <0>;
pit-period = <1000000>;
clock-frequency = <60000000>;
label = "PIT0";
};
};
};
&nvic {
arm,num-irq-priority-bits = <4>;
};
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