102 lines
1.9 KiB
Plaintext
102 lines
1.9 KiB
Plaintext
/*
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* Copyright (c) 2019 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv8-m.dtsi>
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#include "nrf_common.dtsi"
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m33f";
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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swo-ref-frequency = <64000000>;
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mpu: mpu@e000ed90 {
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compatible = "arm,armv8m-mpu";
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reg = <0xe000ed90 0x40>;
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};
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};
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};
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chosen {
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zephyr,flash-controller = &flash_controller;
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};
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soc {
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sram0: memory@20000000 {
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compatible = "mmio-sram";
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};
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sram1: memory@21000000 {
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compatible = "mmio-sram";
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};
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peripheral@50000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x50000000 0x10000000>;
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/* Common nRF5340 Application MCU
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* peripheral description
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*/
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#include "nrf5340_cpuapp_peripherals.dtsi"
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};
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/* Additional Secure peripherals */
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cryptocell: crypto@50844000 {
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compatible = "nordic,nrf-cc312";
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reg = <0x50844000 0x1000>;
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label = "CRYPTOCELL";
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status = "okay";
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#address-cells = <1>;
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#size-cells = <1>;
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cryptocell312: crypto@50845000 {
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compatible = "arm,cryptocell-312";
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reg = <0x50845000 0x1000>;
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interrupts = <68 NRF_DEFAULT_IRQ_PRIORITY>;
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label = "CRYPTOCELL312";
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};
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};
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gpiote: gpiote@5000d000 {
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compatible = "nordic,nrf-gpiote";
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reg = <0x5000d000 0x1000>;
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interrupts = <13 5>;
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status = "disabled";
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label = "GPIOTE_0";
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};
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spu: spu@50003000 {
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compatible = "nordic,nrf-spu";
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reg = <0x50003000 0x1000>;
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interrupts = <3 NRF_DEFAULT_IRQ_PRIORITY>;
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status = "okay";
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};
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ficr: ficr@ff0000 {
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compatible = "nordic,nrf-ficr";
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reg = <0xff0000 0x1000>;
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status = "okay";
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};
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uicr: uicr@ff8000 {
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compatible = "nordic,nrf-uicr";
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reg = <0xff8000 0x1000>;
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status = "okay";
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <3>;
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};
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