65 lines
1.7 KiB
ArmAsm
65 lines
1.7 KiB
ArmAsm
/* sw_isr_table.S - ISR table for static ISR declarations for ARC */
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/*
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* Copyright (c) 2015 Intel Corporation
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#define _ASMLANGUAGE
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#include <toolchain.h>
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#include <sections.h>
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#include <arch/cpu.h>
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/*
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* enable preprocessor features, such
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* as %expr - evaluate the expression and use it as a string
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*/
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.altmacro
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/*
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* Define an ISR table entry
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* Define symbol as weak and give the section .gnu.linkonce
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* prefix. This allows linker overload the symbol and the
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* whole section by the one defined by a device driver
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*/
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.macro _isr_table_entry_declare index
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WDATA(_isr_irq\index)
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.section .gnu.linkonce.isr_irq\index
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_isr_irq\index: .word 0xABAD1DEA, _irq_spurious
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.endm
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/*
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* Declare the ISR table
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*/
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.macro _isr_table_declare from, to
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counter = \from
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.rept (\to - \from)
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_isr_table_entry_declare %counter
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counter = counter + 1
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.endr
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.endm
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GTEXT(_irq_spurious)
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GDATA(_sw_isr_table)
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.section .isr_irq16
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.align
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_sw_isr_table:
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/*In ARC architecture, IRQ 0-15 are reserved for the system and are not
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assignable by the user, for that reason the isr table linker section
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start at IRQ 16*/
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_isr_table_declare 16 CONFIG_NUM_IRQS
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