71 lines
1.9 KiB
C
71 lines
1.9 KiB
C
/*
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* Copyright (c) 2017 Linaro Limited
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*
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* Initial contents based on soc/soc_legacy/arm/ti_lm3s6965/soc.c which is:
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* Copyright (c) 2013-2015 Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/drivers/gpio/gpio_mmio32.h>
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#include <soc.h>
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#include <zephyr/linker/linker-defs.h>
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/* Setup GPIO drivers for accessing FPGAIO registers */
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#define FPGAIO_NODE(n) DT_INST(n, arm_mps2_fpgaio_gpio)
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#define FPGAIO_INIT(n) \
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GPIO_MMIO32_INIT(FPGAIO_NODE(n), \
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DT_REG_ADDR(FPGAIO_NODE(n)), \
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BIT_MASK(DT_PROP(FPGAIO_NODE(n), ngpios)))
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/* We expect there to be 3 arm,mps2-fpgaio-gpio devices:
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* led0, button, and misc
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*/
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FPGAIO_INIT(0);
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FPGAIO_INIT(1);
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FPGAIO_INIT(2);
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/* (Secure System Control) Base Address */
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#define SSE_200_SYSTEM_CTRL_S_BASE (0x50021000UL)
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#define SSE_200_SYSTEM_CTRL_INITSVTOR1 (SSE_200_SYSTEM_CTRL_S_BASE + 0x114)
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#define SSE_200_SYSTEM_CTRL_CPU_WAIT (SSE_200_SYSTEM_CTRL_S_BASE + 0x118)
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#define SSE_200_CPU_ID_UNIT_BASE (0x5001F000UL)
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/* The base address that the application image will start at on the secondary
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* (non-TrustZone) Cortex-M33 mcu.
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*/
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#define CPU1_FLASH_ADDRESS (0x38B000)
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/* The memory map offset for the application image, which is used
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* to determine the location of the reset vector at startup.
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*/
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#define CPU1_FLASH_OFFSET (0x10000000)
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/**
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* @brief Wake up CPU 1 from another CPU, this is platform specific.
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*/
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void wakeup_cpu1(void)
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{
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/* Set the Initial Secure Reset Vector Register for CPU 1 */
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*(uint32_t *)(SSE_200_SYSTEM_CTRL_INITSVTOR1) =
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(uint32_t)_vector_start +
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CPU1_FLASH_ADDRESS -
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CPU1_FLASH_OFFSET;
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/* Set the CPU Boot wait control after reset */
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*(uint32_t *)(SSE_200_SYSTEM_CTRL_CPU_WAIT) = 0;
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}
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/**
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* @brief Get the current CPU ID, this is platform specific.
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*
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* @return Current CPU ID
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*/
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uint32_t sse_200_platform_get_cpu_id(void)
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{
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volatile uint32_t *p_cpu_id = (volatile uint32_t *)SSE_200_CPU_ID_UNIT_BASE;
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return (uint32_t)*p_cpu_id;
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}
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