140 lines
4.8 KiB
C
140 lines
4.8 KiB
C
/*
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* Copyright 2022-2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_DRIVERS_ETHERNET_ETH_NXP_S32_NETC_PRIV_H_
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#define ZEPHYR_DRIVERS_ETHERNET_ETH_NXP_S32_NETC_PRIV_H_
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#define NETC_F3_PSICFGR0_SIVC_CVLAN_BIT BIT(0) /* 0x8100 */
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#define NETC_F3_PSICFGR0_SIVC_SVLAN_BIT BIT(1) /* 0x88A8 */
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#define NETC_MIN_RING_LEN 8U
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#define NETC_MIN_RING_BUF_SIZE 64U
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#define NETC_SWITCH_IDX 0U
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#define NETC_SWITCH_PORT_IDX 0U
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#define NETC_SWITCH_PORT_AGING 300U
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#define NETC_ETH_0_RX_CLK_IDX 49U
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#define NETC_ETH_1_RX_CLK_IDX 51U
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#define NETC_MSIX_EVENTS_COUNT 2U
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/* Timeout for various operations */
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#define NETC_TIMEOUT K_MSEC(20)
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/* Helper macros to convert from Zephyr PHY speed to NETC baudrate/duplex types */
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#define PHY_TO_NETC_SPEED(x) \
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(PHY_LINK_IS_SPEED_1000M(x) ? ETHTRCV_BAUD_RATE_1000MBIT : \
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(PHY_LINK_IS_SPEED_100M(x) ? ETHTRCV_BAUD_RATE_100MBIT : ETHTRCV_BAUD_RATE_10MBIT))
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#define PHY_TO_NETC_DUPLEX_MODE(x) \
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(PHY_LINK_IS_FULL_DUPLEX(x) ? NETC_ETHSWT_PORT_FULL_DUPLEX : NETC_ETHSWT_PORT_HALF_DUPLEX)
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/*
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* Get the first MRU mailbox address for an specific mbox handle
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* mbox[0] addr = MRU base addr + (channel × channel offset), with channel=1..N
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*/
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#define MRU_CHANNEL_OFFSET 0x1000
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#define MRU_MBOX_ADDR(node, name) \
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(DT_REG_ADDR(DT_MBOX_CTLR_BY_NAME(node, name)) \
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+ ((DT_MBOX_CHANNEL_BY_NAME(node, name) + 1) * MRU_CHANNEL_OFFSET))
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#define NETC_MSIX(node, name, cb) \
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{ \
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.handler = cb, \
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.mbox_spec = MBOX_DT_SPEC_GET(node, name), \
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}
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/* Tx/Rx ENETC ring definitions */
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#define _NETC_RING(n, idx, len, buf_size, prefix1, prefix2) \
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static Netc_Eth_Ip_##prefix1##BDRType nxp_s32_eth##n##_##prefix2##ring##idx##_desc[len] \
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__nocache __aligned(FEATURE_NETC_BUFFDESCR_ALIGNMENT_BYTES); \
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static uint8_t nxp_s32_eth##n##_##prefix2##ring##idx##_buf[len * buf_size] \
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__nocache __aligned(FEATURE_NETC_BUFF_ALIGNMENT_BYTES)
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#define NETC_RX_RING(n, idx, len, buf_size) _NETC_RING(n, idx, len, buf_size, Rx, rx)
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#define NETC_TX_RING(n, idx, len, buf_size) _NETC_RING(n, idx, len, buf_size, Tx, tx)
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/* Helper function to generate an Ethernet MAC address for a given ENETC instance */
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#define FREESCALE_OUI_B0 0x00
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#define FREESCALE_OUI_B1 0x04
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#define FREESCALE_OUI_B2 0x9f
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#define _NETC_GENERATE_MAC_ADDRESS_RANDOM \
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gen_random_mac(mac_addr, FREESCALE_OUI_B0, FREESCALE_OUI_B1, FREESCALE_OUI_B2)
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#define _NETC_GENERATE_MAC_ADDRESS_UNIQUE(n) \
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do { \
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uint32_t id = 0x001100; \
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\
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mac_addr[0] = FREESCALE_OUI_B0; \
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mac_addr[1] = FREESCALE_OUI_B1; \
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/* Set MAC address locally administered bit (LAA) */ \
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mac_addr[2] = FREESCALE_OUI_B2 | 0x02; \
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mac_addr[3] = (id >> 16) & 0xff; \
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mac_addr[4] = (id >> 8) & 0xff; \
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mac_addr[5] = (id + n) & 0xff; \
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} while (0)
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#define NETC_GENERATE_MAC_ADDRESS(n) \
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static void nxp_s32_eth##n##_generate_mac(uint8_t mac_addr[6]) \
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{ \
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COND_CODE_1(DT_INST_PROP(n, zephyr_random_mac_address), \
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(_NETC_GENERATE_MAC_ADDRESS_RANDOM), \
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(COND_CODE_0(DT_INST_NODE_HAS_PROP(n, local_mac_address),\
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(_NETC_GENERATE_MAC_ADDRESS_UNIQUE(n)), \
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(ARG_UNUSED(mac_addr))))); \
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}
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#define NETC_SI_NXP_S32_HW_INSTANCE_CHECK(i, n) \
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((DT_INST_REG_ADDR(n) == IP_NETC__ENETC0_SI##i##_BASE) ? i : 0)
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#define NETC_SI_NXP_S32_HW_INSTANCE(n) \
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LISTIFY(__DEBRACKET FEATURE_NETC_ETH_NUMBER_OF_CTRLS, \
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NETC_SI_NXP_S32_HW_INSTANCE_CHECK, (|), n)
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/* Helper macros to concatenate tokens that require further expansions */
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#define _CONCAT3(a, b, c) DT_CAT3(a, b, c)
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struct nxp_s32_eth_msix {
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void (*handler)(uint8_t chan, const uint32 *buf, uint8_t buf_size);
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struct mbox_dt_spec mbox_spec;
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};
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struct nxp_s32_eth_config {
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const Netc_Eth_Ip_ConfigType netc_cfg;
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Netc_Eth_Ip_MACFilterHashTableEntryType *mac_filter_hash_table;
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uint8_t si_idx;
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uint8_t port_idx;
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const struct device *phy_dev;
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uint8_t tx_ring_idx;
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uint8_t rx_ring_idx;
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void (*generate_mac)(uint8_t *mac_addr);
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struct nxp_s32_eth_msix msix[NETC_MSIX_EVENTS_COUNT];
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const struct pinctrl_dev_config *pincfg;
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};
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struct nxp_s32_eth_data {
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struct net_if *iface;
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uint8_t mac_addr[6];
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struct k_mutex tx_mutex;
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struct k_sem rx_sem;
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struct k_thread rx_thread;
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K_KERNEL_STACK_MEMBER(rx_thread_stack, CONFIG_ETH_NXP_S32_RX_THREAD_STACK_SIZE);
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};
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int nxp_s32_eth_initialize_common(const struct device *dev);
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int nxp_s32_eth_tx(const struct device *dev, struct net_pkt *pkt);
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enum ethernet_hw_caps nxp_s32_eth_get_capabilities(const struct device *dev);
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void nxp_s32_eth_mcast_filter(const struct device *dev, const struct ethernet_filter *filter);
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int nxp_s32_eth_set_config(const struct device *dev, enum ethernet_config_type type,
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const struct ethernet_config *config);
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extern void Netc_Eth_Ip_MSIX_Rx(uint8_t si_idx);
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#endif /* ZEPHYR_DRIVERS_ETHERNET_ETH_NXP_S32_NETC_PRIV_H_ */
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