zephyr/arch/riscv32/core
Andrew Boie 5dcb279df8 debug: add stack sentinel feature
This places a sentinel value at the lowest 4 bytes of a stack
memory region and checks it at various intervals, including when
servicing interrupts or context switching.

This is implemented on all arches except ARC, which supports stack
bounds checking directly in hardware.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2017-05-13 15:14:41 -04:00
..
offsets
Makefile riscv32: enable gen_isr_tables mechanism 2017-02-15 04:49:17 +00:00
cpu_idle.c kernel: remove all remaining references to nanokernel 2017-04-10 20:21:10 +00:00
fatal.c debug: add stack sentinel feature 2017-05-13 15:14:41 -04:00
irq_manage.c arch: convert to using newly introduced integer sized types 2017-04-21 12:08:12 +00:00
irq_offload.c
isr.S debug: add stack sentinel feature 2017-05-13 15:14:41 -04:00
prep_c.c riscv32: fixed build warnings for obj_tracing 2017-03-06 21:57:53 +01:00
reset.S build: add _ASMLANGUAGE to all asm files 2017-01-24 13:34:51 +00:00
swap.S kernel: tickless: Rename _Swap to allow creation of macro 2017-04-27 13:46:26 +00:00
thread.c kernel: add k_thread_create() API 2017-05-11 20:24:22 -04:00