67 lines
1.4 KiB
C
67 lines
1.4 KiB
C
/*
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* Copyright (c) 2020 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/arch/arm/arch.h>
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#include <zephyr/kernel.h>
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#include <zephyr/sys_clock.h>
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#include <zephyr/timing/timing.h>
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#include <soc.h>
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void soc_timing_init(void)
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{
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/* Setup counter */
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B32TMR1_REGS->CTRL = MCHP_BTMR_CTRL_ENABLE |
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MCHP_BTMR_CTRL_AUTO_RESTART |
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MCHP_BTMR_CTRL_COUNT_UP;
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B32TMR1_REGS->PRLD = 0; /* Preload */
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B32TMR1_REGS->CNT = 0; /* Counter value */
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B32TMR1_REGS->IEN = 0; /* Disable interrupt */
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B32TMR1_REGS->STS = 1; /* Clear interrupt */
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}
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void soc_timing_start(void)
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{
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B32TMR1_REGS->CTRL |= MCHP_BTMR_CTRL_START;
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}
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void soc_timing_stop(void)
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{
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B32TMR1_REGS->CTRL &= ~MCHP_BTMR_CTRL_START;
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}
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timing_t soc_timing_counter_get(void)
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{
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return B32TMR1_REGS->CNT;
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}
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uint64_t soc_timing_cycles_get(volatile timing_t *const start,
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volatile timing_t *const end)
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{
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return (*end - *start);
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}
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uint64_t soc_timing_freq_get(void)
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{
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return CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC;
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}
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uint64_t soc_timing_cycles_to_ns(uint64_t cycles)
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{
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return (cycles) * (NSEC_PER_SEC) / (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC);
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}
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uint64_t soc_timing_cycles_to_ns_avg(uint64_t cycles, uint32_t count)
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{
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return (uint32_t)soc_timing_cycles_to_ns(cycles) / count;
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}
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uint32_t soc_timing_freq_get_mhz(void)
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{
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return (uint32_t)(soc_timing_freq_get() / 1000000);
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}
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