86 lines
1.9 KiB
C
86 lines
1.9 KiB
C
/*
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* Copyright (c) 2023 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/kernel.h>
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#include <zephyr/drivers/gpio.h>
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#include <soc.h>
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#if defined(CONFIG_SOC_SERIES_NRF52X) || defined(CONFIG_SOC_SERIES_NRF53X)
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#define CPU_CLOCK 64000000U
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#else
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#define CPU_CLOCK CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
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#endif
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#if defined(CONFIG_SOC_SERIES_NRF52X) || defined(CONFIG_SOC_SERIES_NRF53X)
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#define FAST_BITBANG_HW_SUPPORT 1
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#else
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#define FAST_BITBANG_HW_SUPPORT 0
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#endif
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static ALWAYS_INLINE void pin_delay_asm(uint32_t delay)
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{
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#if defined(CONFIG_CPU_CORTEX_M)
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__asm volatile ("movs r3, %[p]\n"
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".start_%=:\n"
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"subs r3, #1\n"
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"bne .start_%=\n"
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:
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: [p] "r" (delay)
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: "r3", "cc"
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);
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#else
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#warning "Pin delay is not defined"
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#endif
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}
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static ALWAYS_INLINE void swdp_ll_pin_input(void *const base, uint8_t pin)
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{
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#if defined(CONFIG_SOC_SERIES_NRF52X) || defined(CONFIG_SOC_SERIES_NRF53X)
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NRF_GPIO_Type * reg = base;
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reg->PIN_CNF[pin] = 0b0000;
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#endif
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}
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static ALWAYS_INLINE void swdp_ll_pin_output(void *const base, uint8_t pin)
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{
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#if defined(CONFIG_SOC_SERIES_NRF52X) || defined(CONFIG_SOC_SERIES_NRF53X)
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NRF_GPIO_Type * reg = base;
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reg->PIN_CNF[pin] = 0b0001;
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#endif
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}
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static ALWAYS_INLINE void swdp_ll_pin_set(void *const base, uint8_t pin)
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{
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#if defined(CONFIG_SOC_SERIES_NRF52X) || defined(CONFIG_SOC_SERIES_NRF53X)
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NRF_GPIO_Type * reg = base;
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reg->OUTSET = BIT(pin);
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#endif
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}
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static ALWAYS_INLINE void swdp_ll_pin_clr(void *const base, uint8_t pin)
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{
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#if defined(CONFIG_SOC_SERIES_NRF52X) || defined(CONFIG_SOC_SERIES_NRF53X)
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NRF_GPIO_Type * reg = base;
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reg->OUTCLR = BIT(pin);
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#endif
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}
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static ALWAYS_INLINE uint32_t swdp_ll_pin_get(void *const base, uint8_t pin)
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{
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#if defined(CONFIG_SOC_SERIES_NRF52X) || defined(CONFIG_SOC_SERIES_NRF53X)
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NRF_GPIO_Type * reg = base;
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return ((reg->IN >> pin) & 1);
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#else
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return 0UL;
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#endif
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}
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