83 lines
1.3 KiB
Plaintext
83 lines
1.3 KiB
Plaintext
/*
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* Copyright 2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <nxp/nxp_mcxn94x.dtsi>
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#include "frdm_mcxn947.dtsi"
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/ {
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model = "NXP FRDM_N94 board";
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compatible = "nxp,mcxn947", "nxp,mcx";
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cpus {
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/delete-node/ cpu@1;
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};
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chosen {
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zephyr,sram = &sram0;
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zephyr,flash = &flash;
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zephyr,flash-controller = &fmu;
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zephyr,code-partition = &slot0_partition;
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zephyr,console = &flexcomm4_lpuart4;
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zephyr,shell-uart = &flexcomm4_lpuart4;
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};
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};
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/*
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* Default for this board is to allocate SRAM0-5 to cpu0 but the
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* application can have an application specific device tree to
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* allocate the SRAM0-7 differently.
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*
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* For example, SRAM0-6 could be allocated to cpu0 with only SRAM7
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* for cpu1. This would require the value of sram0 to have a DT_SIZE_K
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* of 384. You would have to make updates to cpu1 sram settings as well.
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*/
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&sram0 {
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compatible = "mmio-sram";
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reg = <0x20000000 DT_SIZE_K(320)>;
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};
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&gpio4 {
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status = "okay";
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};
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&gpio1 {
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status = "okay";
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};
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&gpio0 {
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status = "okay";
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};
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&green_led {
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status = "okay";
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};
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&red_led {
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status = "okay";
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};
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&user_button_2 {
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status = "okay";
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};
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&flexcomm4 {
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status = "okay";
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};
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&flexcomm4_lpuart4 {
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status = "okay";
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};
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&flexspi {
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status = "okay";
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};
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&w25q64jvssiq {
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status = "okay";
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};
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