127 lines
3.1 KiB
C
127 lines
3.1 KiB
C
/*
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* Copyright (c) 2019 STMicroelectronics.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/kernel.h>
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#include <zephyr/pm/pm.h>
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#include <soc.h>
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#include <zephyr/init.h>
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#include <stm32l4xx_ll_utils.h>
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#include <stm32l4xx_ll_bus.h>
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#include <stm32l4xx_ll_cortex.h>
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#include <stm32l4xx_ll_pwr.h>
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#include <stm32l4xx_ll_rcc.h>
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#include <stm32l4xx_ll_system.h>
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#include <clock_control/clock_stm32_ll_common.h>
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#include <zephyr/drivers/clock_control/stm32_clock_control.h>
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#include <zephyr/logging/log.h>
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LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL);
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/* select MSI as wake-up system clock if configured, HSI otherwise */
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#if STM32_SYSCLK_SRC_MSI
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#define RCC_STOP_WAKEUPCLOCK_SELECTED LL_RCC_STOP_WAKEUPCLOCK_MSI
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#else
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#define RCC_STOP_WAKEUPCLOCK_SELECTED LL_RCC_STOP_WAKEUPCLOCK_HSI
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#endif
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void set_mode_stop(uint8_t substate_id)
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{
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/* ensure the proper wake-up system clock */
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LL_RCC_SetClkAfterWakeFromStop(RCC_STOP_WAKEUPCLOCK_SELECTED);
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switch (substate_id) {
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case 1: /* this corresponds to the STOP0 mode: */
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/* enter STOP0 mode */
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LL_PWR_SetPowerMode(LL_PWR_MODE_STOP0);
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break;
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case 2: /* this corresponds to the STOP1 mode: */
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/* enter STOP1 mode */
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LL_PWR_SetPowerMode(LL_PWR_MODE_STOP1);
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break;
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case 3: /* this corresponds to the STOP2 mode: */
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#ifdef PWR_CR1_RRSTP
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LL_PWR_DisableSRAM3Retention();
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#endif /* PWR_CR1_RRSTP */
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/* enter STOP2 mode */
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LL_PWR_SetPowerMode(LL_PWR_MODE_STOP2);
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break;
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default:
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LOG_DBG("Unsupported power state substate-id %u", substate_id);
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break;
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}
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}
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/* Invoke Low Power/System Off specific Tasks */
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void pm_state_set(enum pm_state state, uint8_t substate_id)
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{
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switch (state) {
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case PM_STATE_SUSPEND_TO_IDLE:
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set_mode_stop(substate_id);
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/* Set SLEEPDEEP bit of Cortex System Control Register */
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LL_LPM_EnableDeepSleep();
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/* Select mode entry : WFE or WFI and enter the CPU selected mode */
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k_cpu_idle();
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break;
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case PM_STATE_STANDBY:
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LL_PWR_SetPowerMode(LL_PWR_MODE_STANDBY);
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LL_LPM_EnableDeepSleep();
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LL_DBGMCU_DisableDBGStandbyMode();
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k_cpu_idle();
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break;
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default:
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LOG_DBG("Unsupported power state %u", state);
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return;
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}
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}
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/* Handle SOC specific activity after Low Power Mode Exit */
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void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
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{
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switch (state) {
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case PM_STATE_SUSPEND_TO_IDLE:
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if (substate_id <= 3) {
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LL_LPM_DisableSleepOnExit();
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LL_LPM_EnableSleep();
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} else {
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LOG_DBG("Unsupported power substate-id %u",
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substate_id);
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}
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/* need to restore the clock */
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stm32_clock_control_init(NULL);
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/*
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* System is now in active mode.
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* Reenable interrupts which were disabled
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* when OS started idling code.
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*/
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irq_unlock(0);
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break;
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case PM_STATE_STANDBY:
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__fallthrough;
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case PM_STATE_SUSPEND_TO_RAM:
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__fallthrough;
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case PM_STATE_SUSPEND_TO_DISK:
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__fallthrough;
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default:
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LOG_DBG("Unsupported power state %u", state);
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break;
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}
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}
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/* Initialize STM32 Power */
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static int stm32_power_init(void)
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{
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/* enable Power clock */
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LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
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return 0;
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}
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SYS_INIT(stm32_power_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
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