zephyr/arch/xtensa/core
Andy Ross 0670ba6c92 xtensa: Disable interrupts on entry to _Cstart
Zephyr isn't ready to handle interrupts yet, until the
threading/scheduler are set up and we make our first context switch.
This was a semi-hidden bug: only the timer interrupt would actually
get unmasked before the system was ready, and obviously would never
have time to fire a tick before the system completed initialization.
But a combination of system load and a new version of Qemu (which
seems to be more sensitive to non-deterministic timing glitchery) has
made this visible.  About 2-3% of the time when run under a full
sanitycheck, the qemu process will get swapped away for long enough
that the tick timer expires before _Cstart() has reached
enable_multithreading().

It looks like the original code was cut and pasted from another
implementation, which was expected to call into an "application"
main() routine that wanted interrupts ready.

Fixes #11182

(Note also that this code is not used for ESP-32, which has its own
startup path)

Signed-off-by: Andy Ross <andrew.j.ross@intel.com>
2018-11-12 13:51:20 -05:00
..
offsets
startup
CMakeLists.txt
atomic.S
cpu_idle.c xtensa: removed obsolete headers 2018-09-01 13:58:46 -04:00
crt1.S xtensa: Disable interrupts on entry to _Cstart 2018-11-12 13:51:20 -05:00
fatal.c arch: Add LOG_PANIC to fault handlers 2018-09-27 13:11:26 +05:30
irq_manage.c xtensa: add _arch_irq_connect_dynamic() 2018-11-10 11:01:22 -05:00
irq_offload.c arch: xtensa: include soc.h to fix build errors 2018-11-03 12:40:33 -04:00
swap.S systemview: add support natively using tracing hooks 2018-08-21 05:45:47 -07:00
thread.c coccicnelle: Ignore return of memset 2018-09-14 16:55:37 -04:00
window_vectors.S
xt_zephyr.S
xtensa-asm2-util.S xtensa: specify which SR to store pointer to _kernel.cpu struct 2018-10-19 17:52:45 -04:00
xtensa-asm2.c coccicnelle: Ignore return of memset 2018-09-14 16:55:37 -04:00
xtensa_context.S
xtensa_intgen.py arch: xtensa: Do not generate unused `handle_irq` label unless needed 2018-10-27 21:25:57 -04:00
xtensa_intgen.tmpl
xtensa_intr.c
xtensa_intr_asm.S
xtensa_vectors.S arch: xtensa: remove extra #endif 2018-09-04 14:27:33 -04:00