406 lines
11 KiB
ArmAsm
406 lines
11 KiB
ArmAsm
/*
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* Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define _ASMLANGUAGE
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#include <toolchain.h>
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#include <sections.h>
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#include <kernel_structs.h>
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#include <offsets_short.h>
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/* imports */
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GDATA(_sw_isr_table)
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GTEXT(__soc_save_context)
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GTEXT(__soc_restore_context)
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GTEXT(__soc_is_irq)
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GTEXT(__soc_handle_irq)
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GTEXT(_Fault)
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GTEXT(_k_neg_eagain)
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GTEXT(_is_next_thread_current)
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GTEXT(_get_next_ready_thread)
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#ifdef CONFIG_KERNEL_EVENT_LOGGER_CONTEXT_SWITCH
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GTEXT(_sys_k_event_logger_context_switch)
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#endif
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#ifdef CONFIG_KERNEL_EVENT_LOGGER_SLEEP
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GTEXT(_sys_k_event_logger_exit_sleep)
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#endif
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#ifdef CONFIG_KERNEL_EVENT_LOGGER_INTERRUPT
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GTEXT(_sys_k_event_logger_interrupt)
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#endif
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#ifdef CONFIG_IRQ_OFFLOAD
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GTEXT(_offload_routine)
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#endif
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/* exports */
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GTEXT(__irq_wrapper)
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/* use ABI name of registers for the sake of simplicity */
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/*
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* ISR is handled at both ARCH and SOC levels.
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* At the ARCH level, ISR handles basic context saving/restore of registers
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* onto/from the thread stack and calls corresponding IRQ function registered
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* at driver level.
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* At SOC level, ISR handles saving/restoring of SOC-specific registers
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* onto/from the thread stack (handled via __soc_save_context and
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* __soc_restore_context functions). SOC level save/restore context
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* is accounted for only if CONFIG_RISCV_SOC_CONTEXT_SAVE variable is set
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*
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* Moreover, given that RISC-V architecture does not provide a clear ISA
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* specification about interrupt handling, each RISC-V SOC handles it in
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* its own way. Hence, the generic RISC-V ISR handler expects the following
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* functions to be provided at the SOC level:
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* __soc_is_irq: to check if the exception is the result of an interrupt or not.
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* __soc_handle_irq: handle pending IRQ at SOC level (ex: clear pending IRQ in
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* SOC-specific IRQ register)
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*/
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/*
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* Handler called upon each exception/interrupt/fault
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* In this architecture, system call (ECALL) is used to perform context
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* switching or IRQ offloading (when enabled).
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*/
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SECTION_FUNC(exception.entry, __irq_wrapper)
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/* Allocate space on thread stack to save registers */
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addi sp, sp, -__NANO_ESF_SIZEOF
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/*
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* Save caller-saved registers on current thread stack.
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* NOTE: need to be updated to account for floating-point registers
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* floating-point registers should be accounted for when corresponding
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* config variable is set
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*/
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sw ra, __NANO_ESF_ra_OFFSET(sp)
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sw gp, __NANO_ESF_gp_OFFSET(sp)
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sw tp, __NANO_ESF_tp_OFFSET(sp)
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sw t0, __NANO_ESF_t0_OFFSET(sp)
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sw t1, __NANO_ESF_t1_OFFSET(sp)
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sw t2, __NANO_ESF_t2_OFFSET(sp)
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sw t3, __NANO_ESF_t3_OFFSET(sp)
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sw t4, __NANO_ESF_t4_OFFSET(sp)
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sw t5, __NANO_ESF_t5_OFFSET(sp)
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sw t6, __NANO_ESF_t6_OFFSET(sp)
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sw a0, __NANO_ESF_a0_OFFSET(sp)
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sw a1, __NANO_ESF_a1_OFFSET(sp)
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sw a2, __NANO_ESF_a2_OFFSET(sp)
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sw a3, __NANO_ESF_a3_OFFSET(sp)
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sw a4, __NANO_ESF_a4_OFFSET(sp)
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sw a5, __NANO_ESF_a5_OFFSET(sp)
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sw a6, __NANO_ESF_a6_OFFSET(sp)
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sw a7, __NANO_ESF_a7_OFFSET(sp)
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/* Save MEPC register */
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csrr t0, mepc
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sw t0, __NANO_ESF_mepc_OFFSET(sp)
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/* Save SOC-specific MSTATUS register */
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csrr t0, SOC_MSTATUS_REG
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sw t0, __NANO_ESF_mstatus_OFFSET(sp)
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#ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE
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/* Handle context saving at SOC level. */
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jal ra, __soc_save_context
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#endif /* CONFIG_RISCV_SOC_CONTEXT_SAVE */
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/*
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* Check if exception is the result of an interrupt or not.
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* (SOC dependent). Following the RISC-V architecture spec, the MSB
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* of the mcause register is used to indicate whether an exception
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* is the result of an interrupt or an exception/fault. But for some
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* SOCs (like pulpino or riscv-qemu), the MSB is never set to indicate
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* interrupt. Hence, check for interrupt/exception via the __soc_is_irq
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* function (that needs to be implemented by each SOC). The result is
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* returned via register a0 (1: interrupt, 0 exception)
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*/
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jal ra, __soc_is_irq
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/* If a0 != 0, jump to is_interrupt */
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addi t1, x0, 0
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bnez a0, is_interrupt
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/*
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* If exception is not an interrupt, MEPC will contain
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* the instruction address, which has caused the exception.
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* Increment saved MEPC by 4 to prevent running into the
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* exception again, upon exiting the ISR.
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*/
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lw t0, __NANO_ESF_mepc_OFFSET(sp)
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addi t0, t0, 4
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sw t0, __NANO_ESF_mepc_OFFSET(sp)
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/*
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* If the exception is the result of an ECALL, check whether to
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* perform a context-switch or an IRQ offload. Otherwise call _Fault
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* to report the exception.
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*/
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csrr t0, mcause
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li t2, SOC_MCAUSE_IRQ_MASK
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and t0, t0, t2
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li t1, SOC_MCAUSE_ECALL_EXP
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/*
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* If mcause == SOC_MCAUSE_ECALL_EXP, handle system call,
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* otherwise handle fault
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*/
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#ifdef CONFIG_IRQ_OFFLOAD
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/* If not system call, jump to is_fault */
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bne t0, t1, is_fault
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/*
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* Determine if the system call is the result of an IRQ offloading.
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* Done by checking if _offload_routine is not pointing to NULL.
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* If NULL, jump to reschedule to perform a context-switch, otherwise,
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* jump to is_interrupt to handle the IRQ offload.
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*/
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la t0, _offload_routine
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lw t1, 0x00(t0)
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beqz t1, reschedule
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bnez t1, is_interrupt
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is_fault:
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#else
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/*
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* Go to reschedule to handle context-switch if system call,
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* otherwise call _Fault to handle exception
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*/
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beq t0, t1, reschedule
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#endif
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/*
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* Call _Fault to handle exception.
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* Stack pointer is pointing to a NANO_ESF structure, pass it
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* to _Fault (via register a0).
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* If _Fault shall return, set return address to no_reschedule
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* to restore stack.
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*/
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addi a0, sp, 0
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la ra, no_reschedule
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tail _Fault
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is_interrupt:
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/*
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* Save current thread stack pointer and switch
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* stack pointer to interrupt stack.
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*/
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/* Save thread stack pointer to temp register t0 */
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addi t0, sp, 0
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/* Switch to interrupt stack */
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la t2, _kernel
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lw sp, _kernel_offset_to_irq_stack(t2)
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/*
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* Save thread stack pointer on interrupt stack
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* In RISC-V, stack pointer needs to be 16-byte aligned
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*/
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addi sp, sp, -16
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sw t0, 0x00(sp)
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on_irq_stack:
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/* Increment _kernel.nested variable */
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lw t3, _kernel_offset_to_nested(t2)
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addi t3, t3, 1
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sw t3, _kernel_offset_to_nested(t2)
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/*
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* If we are here due to a system call, t1 register should != 0.
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* In this case, perform IRQ offloading, otherwise jump to call_irq
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*/
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beqz t1, call_irq
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/*
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* Call _irq_do_offload to handle IRQ offloading.
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* Set return address to on_thread_stack in order to jump there
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* upon returning from _irq_do_offload
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*/
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la ra, on_thread_stack
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tail _irq_do_offload
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call_irq:
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#ifdef CONFIG_KERNEL_EVENT_LOGGER_SLEEP
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call _sys_k_event_logger_exit_sleep
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#endif
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#ifdef CONFIG_KERNEL_EVENT_LOGGER_INTERRUPT
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call _sys_k_event_logger_interrupt
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#endif
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/* Get IRQ causing interrupt */
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csrr a0, mcause
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li t0, SOC_MCAUSE_IRQ_MASK
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and a0, a0, t0
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/*
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* Clear pending IRQ generating the interrupt at SOC level
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* Pass IRQ number to __soc_handle_irq via register a0
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*/
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jal ra, __soc_handle_irq
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/*
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* Call corresponding registered function in _sw_isr_table.
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* (table is 8-bytes wide, we should shift index by 3)
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*/
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la t0, _sw_isr_table
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slli a0, a0, 3
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add t0, t0, a0
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/* Load argument in a0 register */
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lw a0, 0x00(t0)
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/* Load ISR function address in register t1 */
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lw t1, 0x04(t0)
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/* Call ISR function */
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jalr ra, t1
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on_thread_stack:
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/* Get reference to _kernel */
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la t1, _kernel
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/* Decrement _kernel.nested variable */
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lw t2, _kernel_offset_to_nested(t1)
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addi t2, t2, -1
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sw t2, _kernel_offset_to_nested(t1)
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/* Restore thread stack pointer */
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lw t0, 0x00(sp)
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addi sp, t0, 0
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#ifdef CONFIG_PREEMPT_ENABLED
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/*
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* Check if we need to perform a reschedule
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*/
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/* Get pointer to _kernel.current */
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lw t2, _kernel_offset_to_current(t1)
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/*
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* If non-preemptible thread, do not schedule
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* (see explanation of preempt field in kernel_structs.h
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*/
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lhu t3, _thread_offset_to_preempt(t2)
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li t4, _NON_PREEMPT_THRESHOLD
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bgeu t3, t4, no_reschedule
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/*
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* Check if next thread to schedule is current thread.
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* If yes do not perform a reschedule
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*/
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lw t3, _kernel_offset_to_ready_q_cache(t1)
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beq t3, t2, no_reschedule
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#else
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j no_reschedule
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#endif /* CONFIG_PREEMPT_ENABLED */
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reschedule:
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#if CONFIG_KERNEL_EVENT_LOGGER_CONTEXT_SWITCH
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call _sys_k_event_logger_context_switch
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#endif /* CONFIG_KERNEL_EVENT_LOGGER_CONTEXT_SWITCH */
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/* Get reference to _kernel */
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la t0, _kernel
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/* Get pointer to _kernel.current */
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lw t1, _kernel_offset_to_current(t0)
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/*
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* Save callee-saved registers of current thread
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* prior to handle context-switching
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*/
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sw s0, _thread_offset_to_s0(t1)
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sw s1, _thread_offset_to_s1(t1)
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sw s2, _thread_offset_to_s2(t1)
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sw s3, _thread_offset_to_s3(t1)
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sw s4, _thread_offset_to_s4(t1)
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sw s5, _thread_offset_to_s5(t1)
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sw s6, _thread_offset_to_s6(t1)
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sw s7, _thread_offset_to_s7(t1)
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sw s8, _thread_offset_to_s8(t1)
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sw s9, _thread_offset_to_s9(t1)
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sw s10, _thread_offset_to_s10(t1)
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sw s11, _thread_offset_to_s11(t1)
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/*
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* Save stack pointer of current thread and set the default return value
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* of _Swap to _k_neg_eagain for the thread.
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*/
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sw sp, _thread_offset_to_sp(t1)
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la t2, _k_neg_eagain
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lw t3, 0x00(t2)
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sw t3, _thread_offset_to_swap_return_value(t1)
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/* Get next thread to schedule. */
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lw t1, _kernel_offset_to_ready_q_cache(t0)
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/*
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* Set _kernel.current to new thread loaded in t1
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*/
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sw t1, _kernel_offset_to_current(t0)
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/* Switch to new thread stack */
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lw sp, _thread_offset_to_sp(t1)
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/* Restore callee-saved registers of new thread */
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lw s0, _thread_offset_to_s0(t1)
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lw s1, _thread_offset_to_s1(t1)
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lw s2, _thread_offset_to_s2(t1)
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lw s3, _thread_offset_to_s3(t1)
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lw s4, _thread_offset_to_s4(t1)
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lw s5, _thread_offset_to_s5(t1)
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lw s6, _thread_offset_to_s6(t1)
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lw s7, _thread_offset_to_s7(t1)
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lw s8, _thread_offset_to_s8(t1)
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lw s9, _thread_offset_to_s9(t1)
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lw s10, _thread_offset_to_s10(t1)
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lw s11, _thread_offset_to_s11(t1)
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no_reschedule:
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#ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE
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/* Restore context at SOC level */
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jal ra, __soc_restore_context
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#endif /* CONFIG_RISCV_SOC_CONTEXT_SAVE */
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/* Restore caller-saved registers from thread stack */
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lw ra, __NANO_ESF_ra_OFFSET(sp)
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lw gp, __NANO_ESF_gp_OFFSET(sp)
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lw tp, __NANO_ESF_tp_OFFSET(sp)
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lw t0, __NANO_ESF_t0_OFFSET(sp)
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lw t1, __NANO_ESF_t1_OFFSET(sp)
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lw t2, __NANO_ESF_t2_OFFSET(sp)
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lw t3, __NANO_ESF_t3_OFFSET(sp)
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lw t4, __NANO_ESF_t4_OFFSET(sp)
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lw t5, __NANO_ESF_t5_OFFSET(sp)
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lw t6, __NANO_ESF_t6_OFFSET(sp)
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lw a0, __NANO_ESF_a0_OFFSET(sp)
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lw a1, __NANO_ESF_a1_OFFSET(sp)
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lw a2, __NANO_ESF_a2_OFFSET(sp)
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lw a3, __NANO_ESF_a3_OFFSET(sp)
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lw a4, __NANO_ESF_a4_OFFSET(sp)
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lw a5, __NANO_ESF_a5_OFFSET(sp)
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lw a6, __NANO_ESF_a6_OFFSET(sp)
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lw a7, __NANO_ESF_a7_OFFSET(sp)
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/* Restore MEPC register */
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lw t0, __NANO_ESF_mepc_OFFSET(sp)
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csrw mepc, t0
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/* Restore SOC-specific MSTATUS register */
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lw t0, __NANO_ESF_mstatus_OFFSET(sp)
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csrw SOC_MSTATUS_REG, t0
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/* Release stack space */
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addi sp, sp, __NANO_ESF_SIZEOF
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/* Call SOC_ERET to exit ISR */
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SOC_ERET
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