96 lines
1.6 KiB
Plaintext
96 lines
1.6 KiB
Plaintext
# Copyright (c) 2017 Intel Corporation
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#
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# SPDX-License-Identifier: Apache-2.0
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if BOARD_INTEL_S1000_CRB
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config BOARD
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default "intel_s1000_crb"
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config BOARD_XTENSA
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def_bool y
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config CAVS_ICTL_0_OFFSET
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default 0x06
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config CAVS_ICTL_1_OFFSET
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default 0x0A
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config CAVS_ICTL_2_OFFSET
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default 0x0D
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config CAVS_ICTL_3_OFFSET
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default 0x10
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config DW_ICTL_OFFSET
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default 0x07
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config 2ND_LVL_INTR_00_OFFSET
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default CAVS_ICTL_0_OFFSET
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config 2ND_LVL_INTR_01_OFFSET
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default CAVS_ICTL_1_OFFSET
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config 2ND_LVL_INTR_02_OFFSET
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default CAVS_ICTL_2_OFFSET
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config 2ND_LVL_INTR_03_OFFSET
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default CAVS_ICTL_3_OFFSET
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config 3RD_LVL_INTR_00_OFFSET
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default DW_ICTL_OFFSET
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config MAX_IRQ_PER_AGGREGATOR
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default 32
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config NUM_2ND_LEVEL_AGGREGATORS
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default 4
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config NUM_3RD_LEVEL_AGGREGATORS
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default 1
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config 2ND_LVL_ISR_TBL_OFFSET
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default 21
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config 3RD_LVL_ISR_TBL_OFFSET
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default 149
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config CAVS_ISR_TBL_OFFSET
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default 2ND_LVL_ISR_TBL_OFFSET
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config DW_ISR_TBL_OFFSET
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default 3RD_LVL_ISR_TBL_OFFSET
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config GPIO_DW_0_NAME
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default "GPIO_PORTA"
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config GPIO_DW_0_IRQ_PRI
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default 1
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config I2C_0_DEFAULT_CFG
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default 0x12
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if DMA_CAVS
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config HEAP_MEM_POOL_SIZE
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default 1024
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endif # DMA_CAVS
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if USB
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config USB_DW
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def_bool y
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config USB_DW_IRQ_PRI
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default 3
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config USB_DW_USB_2_0
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def_bool y
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config USB_HID_MAX_PAYLOAD_SIZE
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default 128
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config USB_COMPOSITE_BUFFER_SIZE
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default 128
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endif # USB
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if UART_NS16550
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config UART_NS16550_PORT_0
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def_bool y
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if UART_NS16550_PORT_0
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config UART_NS16550_PORT_0_OPTIONS
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default 0
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config UART_INTERRUPT_DRIVEN
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def_bool y
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endif # UART_NS16550_PORT_0
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endif # UART_NS16550
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endif # BOARD_INTEL_S1000_CRB
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