459 lines
13 KiB
C
459 lines
13 KiB
C
/*
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* Copyright (c) 2020 ITE Corporation. All Rights Reserved.
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT ite_it8xxx2_timer
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#include <zephyr/init.h>
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#include <zephyr/drivers/timer/system_timer.h>
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#include <zephyr/dt-bindings/interrupt-controller/ite-intc.h>
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#include <soc.h>
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#include <zephyr/spinlock.h>
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#include <zephyr/sys_clock.h>
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#include <zephyr/logging/log.h>
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#include <zephyr/irq.h>
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LOG_MODULE_REGISTER(timer, LOG_LEVEL_ERR);
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BUILD_ASSERT(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC == 32768,
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"ITE RTOS timer HW frequency is fixed at 32768Hz");
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/* Event timer configurations */
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#define EVENT_TIMER EXT_TIMER_3
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#define EVENT_TIMER_IRQ DT_INST_IRQ_BY_IDX(0, 0, irq)
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#define EVENT_TIMER_FLAG DT_INST_IRQ_BY_IDX(0, 0, flags)
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/* Event timer max count is 512 sec (base on clock source 32768Hz) */
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#define EVENT_TIMER_MAX_CNT 0x00FFFFFFUL
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/* Busy wait low timer configurations */
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#define BUSY_WAIT_L_TIMER EXT_TIMER_5
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#define BUSY_WAIT_L_TIMER_IRQ DT_INST_IRQ_BY_IDX(0, 2, irq)
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#define BUSY_WAIT_L_TIMER_FLAG DT_INST_IRQ_BY_IDX(0, 2, flags)
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/* Busy wait high timer configurations */
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#define BUSY_WAIT_H_TIMER EXT_TIMER_6
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#define BUSY_WAIT_H_TIMER_IRQ DT_INST_IRQ_BY_IDX(0, 3, irq)
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#define BUSY_WAIT_H_TIMER_FLAG DT_INST_IRQ_BY_IDX(0, 3, flags)
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/* Busy wait high timer max count is 71.58min (base on clock source 1MHz) */
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#define BUSY_WAIT_TIMER_H_MAX_CNT 0xFFFFFFFFUL
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#if defined(CONFIG_TEST)
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const int32_t z_sys_timer_irq_for_test = DT_IRQ_BY_IDX(DT_NODELABEL(timer), 5, irq);
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#endif
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#ifdef CONFIG_SOC_IT8XXX2_PLL_FLASH_48M
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/*
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* One shot timer configurations
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*
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* NOTE: Timer1/2 register address isn't regular like timer3/4/5/6/7/8, and
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* timer1 is used for printing watchdog warning message. So now we use
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* timer2 only one shot to wake up chip and change pll.
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*/
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#define WDT_BASE DT_REG_ADDR(DT_NODELABEL(twd0))
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#define WDT_REG (struct wdt_it8xxx2_regs *)(WDT_BASE)
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#define ONE_SHOT_TIMER_IRQ DT_IRQ_BY_IDX(DT_NODELABEL(twd0), 1, irq)
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#define ONE_SHOT_TIMER_FLAG DT_IRQ_BY_IDX(DT_NODELABEL(twd0), 1, flags)
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#endif
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#define MS_TO_COUNT(hz, ms) ((hz) * (ms) / 1000)
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/*
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* One system (kernel) tick is as how much HW timer counts
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*
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* NOTE: Event and free run timer individually select the same clock source
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* frequency, so they can use the same HW_CNT_PER_SYS_TICK to transform
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* unit between HW count and system tick. If clock source frequency is
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* different, then we should define another to transform.
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*/
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#define HW_CNT_PER_SYS_TICK (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC \
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/ CONFIG_SYS_CLOCK_TICKS_PER_SEC)
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/* Event timer max count is as how much system (kernel) tick */
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#define EVEN_TIMER_MAX_CNT_SYS_TICK (EVENT_TIMER_MAX_CNT \
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/ HW_CNT_PER_SYS_TICK)
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static struct k_spinlock lock;
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/* Last HW count that we called sys_clock_announce() */
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static volatile uint32_t last_announced_hw_cnt;
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enum ext_timer_raw_cnt {
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EXT_NOT_RAW_CNT = 0,
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EXT_RAW_CNT,
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};
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enum ext_timer_init {
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EXT_NOT_FIRST_TIME_ENABLE = 0,
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EXT_FIRST_TIME_ENABLE,
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};
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enum ext_timer_int {
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EXT_WITHOUT_TIMER_INT = 0,
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EXT_WITH_TIMER_INT,
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};
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enum ext_timer_start {
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EXT_NOT_START_TIMER = 0,
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EXT_START_TIMER,
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};
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#ifdef CONFIG_SOC_IT8XXX2_PLL_FLASH_48M
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static void timer_5ms_one_shot_isr(const void *unused)
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{
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ARG_UNUSED(unused);
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/*
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* We are here because we have completed changing PLL sequence,
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* so disabled one shot timer interrupt.
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*/
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irq_disable(ONE_SHOT_TIMER_IRQ);
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}
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/*
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* This timer is used to wake up chip from sleep mode to complete
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* changing PLL sequence.
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*/
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void timer_5ms_one_shot(void)
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{
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struct wdt_it8xxx2_regs *const timer2_reg = WDT_REG;
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uint32_t hw_cnt;
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/* Initialize interrupt handler of one shot timer */
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IRQ_CONNECT(ONE_SHOT_TIMER_IRQ, 0, timer_5ms_one_shot_isr, NULL,
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ONE_SHOT_TIMER_FLAG);
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/* Set rising edge triggered of one shot timer */
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ite_intc_irq_polarity_set(ONE_SHOT_TIMER_IRQ, ONE_SHOT_TIMER_FLAG);
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/* Clear interrupt status of one shot timer */
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ite_intc_isr_clear(ONE_SHOT_TIMER_IRQ);
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/* Set clock source of one shot timer */
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timer2_reg->ET2PSR = EXT_PSR_32P768K;
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/*
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* Set count of one shot timer,
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* and after write ET2CNTLLR timer will start
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*/
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hw_cnt = MS_TO_COUNT(32768, 5/*ms*/);
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timer2_reg->ET2CNTLH2R = (uint8_t)((hw_cnt >> 16) & 0xff);
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timer2_reg->ET2CNTLHR = (uint8_t)((hw_cnt >> 8) & 0xff);
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timer2_reg->ET2CNTLLR = (uint8_t)(hw_cnt & 0xff);
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irq_enable(ONE_SHOT_TIMER_IRQ);
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}
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#endif /* CONFIG_SOC_IT8XXX2_PLL_FLASH_48M */
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#ifdef CONFIG_ARCH_HAS_CUSTOM_BUSY_WAIT
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void arch_busy_wait(uint32_t usec_to_wait)
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{
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if (!usec_to_wait) {
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return;
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}
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/* Decrease 1us here to calibrate our access registers latency */
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usec_to_wait--;
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/*
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* We want to set the bit(1) re-start busy wait timer as soon
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* as possible, so we directly write 0xb instead of | bit(1).
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*/
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IT8XXX2_EXT_CTRLX(BUSY_WAIT_L_TIMER) = IT8XXX2_EXT_ETX_COMB_RST_EN;
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for (;;) {
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uint32_t curr = IT8XXX2_EXT_CNTOX(BUSY_WAIT_H_TIMER);
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if (curr >= usec_to_wait) {
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break;
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}
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}
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}
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#endif
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static void evt_timer_enable(void)
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{
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/* Enable and re-start event timer */
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IT8XXX2_EXT_CTRLX(EVENT_TIMER) |= (IT8XXX2_EXT_ETXEN |
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IT8XXX2_EXT_ETXRST);
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}
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static void evt_timer_isr(const void *unused)
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{
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ARG_UNUSED(unused);
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/* Disable event timer */
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IT8XXX2_EXT_CTRLX(EVENT_TIMER) &= ~IT8XXX2_EXT_ETXEN;
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/* W/C event timer interrupt status */
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ite_intc_isr_clear(EVENT_TIMER_IRQ);
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if (IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
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/*
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* Get free run observer count from last time announced and
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* transform unit to system tick
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*/
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uint32_t dticks = (~(IT8XXX2_EXT_CNTOX(FREE_RUN_TIMER)) -
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last_announced_hw_cnt) / HW_CNT_PER_SYS_TICK;
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last_announced_hw_cnt += (dticks * HW_CNT_PER_SYS_TICK);
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sys_clock_announce(dticks);
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} else {
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/* enable event timer */
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evt_timer_enable();
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/* Informs kernel that one system tick has elapsed */
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sys_clock_announce(1);
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}
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}
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static void free_run_timer_overflow_isr(const void *unused)
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{
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ARG_UNUSED(unused);
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/* Read to clear terminal count flag */
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__unused uint8_t rc_tc = IT8XXX2_EXT_CTRLX(FREE_RUN_TIMER);
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/*
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* TODO: to increment 32-bit "top half" here for software 64-bit
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* timer emulation.
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*/
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}
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void sys_clock_set_timeout(int32_t ticks, bool idle)
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{
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uint32_t hw_cnt;
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ARG_UNUSED(idle);
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if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
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/* Always return for non-tickless kernel system */
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return;
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}
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/* Critical section */
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k_spinlock_key_t key = k_spin_lock(&lock);
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/* Disable event timer */
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IT8XXX2_EXT_CTRLX(EVENT_TIMER) &= ~IT8XXX2_EXT_ETXEN;
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if (ticks == K_TICKS_FOREVER) {
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/*
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* If kernel doesn't have a timeout:
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* 1.CONFIG_SYSTEM_CLOCK_SLOPPY_IDLE = y (no future timer interrupts
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* are expected), kernel pass K_TICKS_FOREVER (0xFFFF FFFF FFFF FFFF),
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* we handle this case in here.
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* 2.CONFIG_SYSTEM_CLOCK_SLOPPY_IDLE = n (schedule timeout as far
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* into the future as possible), kernel pass INT_MAX (0x7FFF FFFF),
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* we handle it in later else {}.
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*/
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k_spin_unlock(&lock, key);
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return;
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} else if (ticks <= 1) {
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/*
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* Ticks <= 1 means the kernel wants the tick announced
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* as soon as possible, ideally no more than one system tick
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* in the future. So set event timer count to 1 system tick or
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* at least 1 hw count.
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*/
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hw_cnt = MAX((1 * HW_CNT_PER_SYS_TICK), 1);
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} else {
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/*
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* Set event timer count to EVENT_TIMER_MAX_CNT, after
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* interrupt fired the remaining time will be set again
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* by sys_clock_announce().
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*/
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hw_cnt = MIN((ticks * HW_CNT_PER_SYS_TICK), EVENT_TIMER_MAX_CNT);
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}
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/* Set event timer 24-bit count */
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IT8XXX2_EXT_CNTX(EVENT_TIMER) = hw_cnt;
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/* W/C event timer interrupt status */
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ite_intc_isr_clear(EVENT_TIMER_IRQ);
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/* enable event timer */
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evt_timer_enable();
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k_spin_unlock(&lock, key);
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LOG_DBG("timeout is 0x%x, set hw count 0x%x", ticks, hw_cnt);
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}
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uint32_t sys_clock_elapsed(void)
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{
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if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
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/* Always return 0 for non-tickless kernel system */
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return 0;
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}
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/* Critical section */
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k_spinlock_key_t key = k_spin_lock(&lock);
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/*
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* Get free run observer count from last time announced and transform
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* unit to system tick
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*/
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uint32_t dticks = (~(IT8XXX2_EXT_CNTOX(FREE_RUN_TIMER)) -
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last_announced_hw_cnt) / HW_CNT_PER_SYS_TICK;
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k_spin_unlock(&lock, key);
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return dticks;
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}
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uint32_t sys_clock_cycle_get_32(void)
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{
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/*
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* Get free run observer count
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*
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* NOTE: Timer is counting down from 0xffffffff. In not combined
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* mode, the observer count value is the same as count, so after
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* NOT count operation we can get counting up value; In
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* combined mode, the observer count value is the same as NOT
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* count operation.
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*/
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uint32_t dticks = ~(IT8XXX2_EXT_CNTOX(FREE_RUN_TIMER));
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return dticks;
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}
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static int timer_init(enum ext_timer_idx ext_timer,
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enum ext_clk_src_sel clock_source_sel,
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enum ext_timer_raw_cnt raw,
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uint32_t ms,
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enum ext_timer_init first_time_enable,
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uint32_t irq_num,
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uint32_t irq_flag,
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enum ext_timer_int with_int,
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enum ext_timer_start start)
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{
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uint32_t hw_cnt;
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if (raw == EXT_RAW_CNT) {
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hw_cnt = ms;
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} else {
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if (clock_source_sel == EXT_PSR_32P768K)
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hw_cnt = MS_TO_COUNT(32768, ms);
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else if (clock_source_sel == EXT_PSR_1P024K)
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hw_cnt = MS_TO_COUNT(1024, ms);
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else if (clock_source_sel == EXT_PSR_32)
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hw_cnt = MS_TO_COUNT(32, ms);
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else if (clock_source_sel == EXT_PSR_8M)
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hw_cnt = 8000 * ms;
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else {
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LOG_ERR("Timer %d clock source error !", ext_timer);
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return -1;
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}
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}
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if (hw_cnt == 0) {
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LOG_ERR("Timer %d count shouldn't be 0 !", ext_timer);
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return -1;
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}
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if (first_time_enable == EXT_FIRST_TIME_ENABLE) {
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/* Enable and re-start external timer x */
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IT8XXX2_EXT_CTRLX(ext_timer) |= (IT8XXX2_EXT_ETXEN |
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IT8XXX2_EXT_ETXRST);
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/* Disable external timer x */
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IT8XXX2_EXT_CTRLX(ext_timer) &= ~IT8XXX2_EXT_ETXEN;
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}
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/* Set rising edge triggered of external timer x */
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ite_intc_irq_polarity_set(irq_num, irq_flag);
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/* Clear interrupt status of external timer x */
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ite_intc_isr_clear(irq_num);
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/* Set clock source of external timer x */
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IT8XXX2_EXT_PSRX(ext_timer) = clock_source_sel;
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/* Set count of external timer x */
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IT8XXX2_EXT_CNTX(ext_timer) = hw_cnt;
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/* Disable external timer x */
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IT8XXX2_EXT_CTRLX(ext_timer) &= ~IT8XXX2_EXT_ETXEN;
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if (start == EXT_START_TIMER)
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/* Enable and re-start external timer x */
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IT8XXX2_EXT_CTRLX(ext_timer) |= (IT8XXX2_EXT_ETXEN |
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IT8XXX2_EXT_ETXRST);
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if (with_int == EXT_WITH_TIMER_INT) {
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irq_enable(irq_num);
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} else {
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irq_disable(irq_num);
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}
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return 0;
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}
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static int sys_clock_driver_init(void)
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{
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int ret;
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/* Enable 32-bit free run timer overflow interrupt */
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IRQ_CONNECT(FREE_RUN_TIMER_IRQ, 0, free_run_timer_overflow_isr, NULL,
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FREE_RUN_TIMER_FLAG);
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/* Set 32-bit timer4 for free run*/
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ret = timer_init(FREE_RUN_TIMER, EXT_PSR_32P768K, EXT_RAW_CNT,
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FREE_RUN_TIMER_MAX_CNT, EXT_FIRST_TIME_ENABLE,
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FREE_RUN_TIMER_IRQ, FREE_RUN_TIMER_FLAG,
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EXT_WITH_TIMER_INT, EXT_START_TIMER);
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if (ret < 0) {
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LOG_ERR("Init free run timer failed");
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return ret;
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}
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/* Set 24-bit timer3 for timeout event */
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IRQ_CONNECT(EVENT_TIMER_IRQ, 0, evt_timer_isr, NULL, EVENT_TIMER_FLAG);
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if (IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
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ret = timer_init(EVENT_TIMER, EXT_PSR_32P768K, EXT_RAW_CNT,
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EVENT_TIMER_MAX_CNT, EXT_FIRST_TIME_ENABLE,
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EVENT_TIMER_IRQ, EVENT_TIMER_FLAG,
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EXT_WITH_TIMER_INT, EXT_NOT_START_TIMER);
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} else {
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/* Start a event timer in one system tick */
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ret = timer_init(EVENT_TIMER, EXT_PSR_32P768K, EXT_RAW_CNT,
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MAX((1 * HW_CNT_PER_SYS_TICK), 1),
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EXT_FIRST_TIME_ENABLE, EVENT_TIMER_IRQ,
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EVENT_TIMER_FLAG, EXT_WITH_TIMER_INT,
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EXT_START_TIMER);
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}
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if (ret < 0) {
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LOG_ERR("Init event timer failed");
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return ret;
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}
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if (IS_ENABLED(CONFIG_ARCH_HAS_CUSTOM_BUSY_WAIT)) {
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/* Set timer5 and timer6 combinational mode for busy wait */
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IT8XXX2_EXT_CTRLX(BUSY_WAIT_L_TIMER) |= IT8XXX2_EXT_ETXCOMB;
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/* Set 32-bit timer6 to count-- every 1us */
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ret = timer_init(BUSY_WAIT_H_TIMER, EXT_PSR_8M, EXT_RAW_CNT,
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BUSY_WAIT_TIMER_H_MAX_CNT, EXT_FIRST_TIME_ENABLE,
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BUSY_WAIT_H_TIMER_IRQ, BUSY_WAIT_H_TIMER_FLAG,
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EXT_WITHOUT_TIMER_INT, EXT_START_TIMER);
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if (ret < 0) {
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LOG_ERR("Init busy wait high timer failed");
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return ret;
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}
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/*
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* Set 24-bit timer5 to overflow every 1us
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* NOTE: When the timer5 count down to overflow in combinational
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* mode, timer6 counter will automatically decrease one count
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* and timer5 will automatically re-start counting down
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* from 0x7. Timer5 clock source is 8MHz (=0.125ns), so the
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* time period from 0x7 to overflow is 0.125ns * 8 = 1us.
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*/
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ret = timer_init(BUSY_WAIT_L_TIMER, EXT_PSR_8M, EXT_RAW_CNT,
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0x7, EXT_FIRST_TIME_ENABLE,
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BUSY_WAIT_L_TIMER_IRQ, BUSY_WAIT_L_TIMER_FLAG,
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EXT_WITHOUT_TIMER_INT, EXT_START_TIMER);
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if (ret < 0) {
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LOG_ERR("Init busy wait low timer failed");
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return ret;
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}
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}
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return 0;
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}
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SYS_INIT(sys_clock_driver_init, PRE_KERNEL_2,
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CONFIG_SYSTEM_CLOCK_INIT_PRIORITY);
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