672 lines
15 KiB
C
672 lines
15 KiB
C
/*
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* Copyright (c) 2019 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT microchip_xec_i2c
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#include <drivers/clock_control.h>
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#include <kernel.h>
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#include <soc.h>
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#include <errno.h>
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#include <drivers/i2c.h>
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#include <logging/log.h>
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LOG_MODULE_REGISTER(i2c_mchp, CONFIG_I2C_LOG_LEVEL);
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#define SPEED_100KHZ_BUS 0
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#define SPEED_400KHZ_BUS 1
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#define SPEED_1MHZ_BUS 2
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#define EC_OWN_I2C_ADDR 0x7F
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#define RESET_WAIT_US 20
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/* I2C timeout is 10 ms (WAIT_INTERVAL * WAIT_COUNT) */
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#define WAIT_INTERVAL 50
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#define WAIT_COUNT 200
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/* I2C Read/Write bit pos */
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#define I2C_READ_WRITE_POS 0
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struct xec_speed_cfg {
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uint32_t bus_clk;
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uint32_t data_timing;
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uint32_t start_hold_time;
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uint32_t config;
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uint32_t timeout_scale;
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};
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struct i2c_xec_config {
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uint32_t port_sel;
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uint32_t base_addr;
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uint8_t girq_id;
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uint8_t girq_bit;
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void (*irq_config_func)(void);
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};
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struct i2c_xec_data {
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uint32_t pending_stop;
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uint32_t speed_id;
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struct i2c_slave_config *slave_cfg;
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bool slave_attached;
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bool slave_read;
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};
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/* Recommended programming values based on 16MHz
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* i2c_baud_clk_period/bus_clk_period - 2 = (low_period + hi_period)
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* bus_clk_reg (16MHz/100KHz -2) = 0x4F + 0x4F
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* (16MHz/400KHz -2) = 0x0F + 0x17
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* (16MHz/1MHz -2) = 0x05 + 0x09
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*/
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static const struct xec_speed_cfg xec_cfg_params[] = {
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[SPEED_100KHZ_BUS] = {
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.bus_clk = 0x00004F4F,
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.data_timing = 0x0C4D5006,
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.start_hold_time = 0x0000004D,
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.config = 0x01FC01ED,
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.timeout_scale = 0x4B9CC2C7,
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},
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[SPEED_400KHZ_BUS] = {
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.bus_clk = 0x00000F17,
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.data_timing = 0x040A0A06,
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.start_hold_time = 0x0000000A,
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.config = 0x01000050,
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.timeout_scale = 0x159CC2C7,
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},
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[SPEED_1MHZ_BUS] = {
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.bus_clk = 0x00000509,
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.data_timing = 0x04060601,
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.start_hold_time = 0x00000006,
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.config = 0x10000050,
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.timeout_scale = 0x089CC2C7,
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},
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};
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static void i2c_xec_reset_config(const struct device *dev)
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{
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const struct i2c_xec_config *config =
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(const struct i2c_xec_config *const) (dev->config);
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struct i2c_xec_data *data =
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(struct i2c_xec_data *const) (dev->data);
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uint32_t ba = config->base_addr;
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/* Assert RESET and clr others */
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MCHP_I2C_SMB_CFG(ba) = MCHP_I2C_SMB_CFG_RESET;
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k_busy_wait(RESET_WAIT_US);
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/* Bus reset */
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MCHP_I2C_SMB_CFG(ba) = 0;
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/* Write 0x80. i.e Assert PIN bit, ESO = 0 and Interrupts
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* disabled (ENI)
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*/
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MCHP_I2C_SMB_CTRL_WO(ba) = MCHP_I2C_SMB_CTRL_PIN;
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/* Enable controller and I2C filters */
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MCHP_I2C_SMB_CFG(ba) = MCHP_I2C_SMB_CFG_GC_EN |
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MCHP_I2C_SMB_CFG_ENAB |
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MCHP_I2C_SMB_CFG_FEN |
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(config->port_sel &
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MCHP_I2C_SMB_CFG_PORT_SEL_MASK);
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/* Configure bus clock register, Data Timing register,
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* Repeated Start Hold Time register,
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* and Timeout Scaling register
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*/
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MCHP_I2C_SMB_BUS_CLK(ba) = xec_cfg_params[data->speed_id].bus_clk;
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MCHP_I2C_SMB_DATA_TM(ba) = xec_cfg_params[data->speed_id].data_timing;
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MCHP_I2C_SMB_RSHT(ba) =
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xec_cfg_params[data->speed_id].start_hold_time;
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MCHP_I2C_SMB_TMTSC(ba) = xec_cfg_params[data->speed_id].timeout_scale;
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MCHP_I2C_SMB_CTRL_WO(ba) = MCHP_I2C_SMB_CTRL_PIN |
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MCHP_I2C_SMB_CTRL_ESO |
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MCHP_I2C_SMB_CTRL_ACK;
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k_busy_wait(RESET_WAIT_US);
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}
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static int xec_spin_yield(int *counter)
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{
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*counter = *counter + 1;
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if (*counter > WAIT_COUNT) {
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return -ETIMEDOUT;
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}
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k_busy_wait(WAIT_INTERVAL);
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return 0;
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}
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static void cleanup_registers(uint32_t ba)
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{
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uint32_t cfg = MCHP_I2C_SMB_CFG(ba);
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cfg |= MCHP_I2C_SMB_CFG_FLUSH_MXBUF_WO;
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MCHP_I2C_SMB_CFG(ba) = cfg;
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cfg &= ~MCHP_I2C_SMB_CFG_FLUSH_MXBUF_WO;
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cfg |= MCHP_I2C_SMB_CFG_FLUSH_MRBUF_WO;
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MCHP_I2C_SMB_CFG(ba) = cfg;
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cfg &= ~MCHP_I2C_SMB_CFG_FLUSH_MRBUF_WO;
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cfg |= MCHP_I2C_SMB_CFG_FLUSH_SXBUF_WO;
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MCHP_I2C_SMB_CFG(ba) = cfg;
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cfg &= ~MCHP_I2C_SMB_CFG_FLUSH_SXBUF_WO;
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cfg |= MCHP_I2C_SMB_CFG_FLUSH_SRBUF_WO;
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MCHP_I2C_SMB_CFG(ba) = cfg;
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cfg &= ~MCHP_I2C_SMB_CFG_FLUSH_SRBUF_WO;
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}
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#ifdef CONFIG_I2C_SLAVE
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static void restart_slave(uint32_t ba)
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{
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MCHP_I2C_SMB_CTRL_WO(ba) = MCHP_I2C_SMB_CTRL_PIN |
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MCHP_I2C_SMB_CTRL_ESO |
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MCHP_I2C_SMB_CTRL_ACK |
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MCHP_I2C_SMB_CTRL_ENI;
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}
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#endif
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static void recover_from_error(const struct device *dev)
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{
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const struct i2c_xec_config *config =
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(const struct i2c_xec_config *const) (dev->config);
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uint32_t ba = config->base_addr;
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cleanup_registers(ba);
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i2c_xec_reset_config(dev);
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}
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static int wait_bus_free(const struct device *dev)
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{
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const struct i2c_xec_config *config =
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(const struct i2c_xec_config *const) (dev->config);
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int ret;
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int counter = 0;
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uint32_t ba = config->base_addr;
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while (!(MCHP_I2C_SMB_STS_RO(ba) & MCHP_I2C_SMB_STS_NBB)) {
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ret = xec_spin_yield(&counter);
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if (ret < 0) {
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return ret;
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}
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}
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/* Check for bus error */
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if (MCHP_I2C_SMB_STS_RO(ba) & MCHP_I2C_SMB_STS_BER) {
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recover_from_error(dev);
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return -EBUSY;
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}
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return 0;
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}
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static int wait_completion(const struct device *dev)
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{
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const struct i2c_xec_config *config =
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(const struct i2c_xec_config *const) (dev->config);
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int ret;
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int counter = 0;
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uint32_t ba = config->base_addr;
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/* Wait for transaction to be completed */
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while (MCHP_I2C_SMB_STS_RO(ba) & MCHP_I2C_SMB_STS_PIN) {
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ret = xec_spin_yield(&counter);
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if (ret < 0) {
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if (MCHP_I2C_SMB_STS_RO(ba) & MCHP_I2C_SMB_STS_PIN) {
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recover_from_error(dev);
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return ret;
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}
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}
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}
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/* Check if Slave send ACK/NACK */
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if (MCHP_I2C_SMB_STS_RO(ba) & MCHP_I2C_SMB_STS_LRB_AD0) {
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recover_from_error(dev);
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return -EIO;
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}
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/* Check for bus error */
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if (MCHP_I2C_SMB_STS_RO(ba) & MCHP_I2C_SMB_STS_BER) {
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recover_from_error(dev);
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return -EBUSY;
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}
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return 0;
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}
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static bool check_lines(uint32_t ba)
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{
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return ((!(MCHP_I2C_SMB_BB_CTRL(ba) & MCHP_I2C_SMB_BB_CLKI_RO)) ||
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(!(MCHP_I2C_SMB_BB_CTRL(ba) & MCHP_I2C_SMB_BB_DATI_RO)));
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}
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static int i2c_xec_configure(const struct device *dev,
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uint32_t dev_config_raw)
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{
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struct i2c_xec_data *data =
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(struct i2c_xec_data *const) (dev->data);
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if (!(dev_config_raw & I2C_MODE_MASTER)) {
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return -ENOTSUP;
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}
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if (dev_config_raw & I2C_ADDR_10_BITS) {
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return -ENOTSUP;
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}
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switch (I2C_SPEED_GET(dev_config_raw)) {
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case I2C_SPEED_STANDARD:
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data->speed_id = SPEED_100KHZ_BUS;
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break;
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case I2C_SPEED_FAST:
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data->speed_id = SPEED_400KHZ_BUS;
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break;
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case I2C_SPEED_FAST_PLUS:
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data->speed_id = SPEED_1MHZ_BUS;
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break;
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default:
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return -EINVAL;
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}
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i2c_xec_reset_config(dev);
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return 0;
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}
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static int i2c_xec_poll_write(const struct device *dev, struct i2c_msg msg,
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uint16_t addr)
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{
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const struct i2c_xec_config *config =
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(const struct i2c_xec_config *const) (dev->config);
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struct i2c_xec_data *data =
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(struct i2c_xec_data *const) (dev->data);
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uint32_t ba = config->base_addr;
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int ret;
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if (data->pending_stop == 0) {
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/* Check clock and data lines */
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if (check_lines(ba)) {
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return -EBUSY;
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}
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/* Wait until bus is free */
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ret = wait_bus_free(dev);
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if (ret) {
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return ret;
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}
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/* Send slave address */
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MCHP_I2C_SMB_DATA(ba) = (addr & ~BIT(0));
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/* Send start and ack bits */
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MCHP_I2C_SMB_CTRL_WO(ba) = MCHP_I2C_SMB_CTRL_PIN |
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MCHP_I2C_SMB_CTRL_ESO | MCHP_I2C_SMB_CTRL_STA |
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MCHP_I2C_SMB_CTRL_ACK;
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ret = wait_completion(dev);
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if (ret) {
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return ret;
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}
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}
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/* Send bytes */
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for (int i = 0U; i < msg.len; i++) {
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MCHP_I2C_SMB_DATA(ba) = msg.buf[i];
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ret = wait_completion(dev);
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if (ret) {
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return ret;
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}
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/* Handle stop bit for last byte to write */
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if (i == (msg.len - 1)) {
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if (msg.flags & I2C_MSG_STOP) {
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/* Send stop and ack bits */
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MCHP_I2C_SMB_CTRL_WO(ba) =
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MCHP_I2C_SMB_CTRL_PIN |
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MCHP_I2C_SMB_CTRL_ESO |
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MCHP_I2C_SMB_CTRL_STO |
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MCHP_I2C_SMB_CTRL_ACK;
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data->pending_stop = 0;
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} else {
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data->pending_stop = 1;
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}
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}
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}
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return 0;
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}
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static int i2c_xec_poll_read(const struct device *dev, struct i2c_msg msg,
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uint16_t addr)
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{
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const struct i2c_xec_config *config =
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(const struct i2c_xec_config *const) (dev->config);
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struct i2c_xec_data *data =
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(struct i2c_xec_data *const) (dev->data);
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uint32_t ba = config->base_addr;
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uint8_t byte, ctrl;
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int ret;
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if (!(msg.flags & I2C_MSG_RESTART)) {
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/* Check clock and data lines */
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if (check_lines(ba)) {
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return -EBUSY;
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}
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/* Wait until bus is free */
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ret = wait_bus_free(dev);
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if (ret) {
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return ret;
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}
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}
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/* MCHP I2C spec recommends that for repeated start to write to control
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* register before writing to data register
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*/
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MCHP_I2C_SMB_CTRL_WO(ba) = MCHP_I2C_SMB_CTRL_ESO |
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MCHP_I2C_SMB_CTRL_STA | MCHP_I2C_SMB_CTRL_ACK;
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/* Send slave address */
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MCHP_I2C_SMB_DATA(ba) = (addr | BIT(0));
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ret = wait_completion(dev);
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if (ret) {
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return ret;
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}
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if (msg.len == 1) {
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/* Send NACK for last transaction */
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MCHP_I2C_SMB_CTRL_WO(ba) = MCHP_I2C_SMB_CTRL_ESO;
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}
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/* Read dummy byte */
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byte = MCHP_I2C_SMB_DATA(ba);
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ret = wait_completion(dev);
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if (ret) {
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return ret;
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}
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for (int i = 0U; i < msg.len; i++) {
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while (MCHP_I2C_SMB_STS_RO(ba) & MCHP_I2C_SMB_STS_PIN) {
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if (MCHP_I2C_SMB_STS_RO(ba) & MCHP_I2C_SMB_STS_BER) {
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recover_from_error(dev);
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return -EBUSY;
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}
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}
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if (i == (msg.len - 1)) {
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if (msg.flags & I2C_MSG_STOP) {
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/* Send stop and ack bits */
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ctrl = (MCHP_I2C_SMB_CTRL_PIN |
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MCHP_I2C_SMB_CTRL_ESO |
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MCHP_I2C_SMB_CTRL_STO |
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MCHP_I2C_SMB_CTRL_ACK);
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MCHP_I2C_SMB_CTRL_WO(ba) = ctrl;
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data->pending_stop = 0;
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}
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} else if (i == (msg.len - 2)) {
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/* Send NACK for last transaction */
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MCHP_I2C_SMB_CTRL_WO(ba) = MCHP_I2C_SMB_CTRL_ESO;
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}
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msg.buf[i] = MCHP_I2C_SMB_DATA(ba);
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}
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return 0;
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}
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static int i2c_xec_transfer(const struct device *dev, struct i2c_msg *msgs,
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uint8_t num_msgs, uint16_t addr)
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{
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int ret = 0;
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#ifdef CONFIG_I2C_SLAVE
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struct i2c_xec_data *data = dev->data;
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if (data->slave_attached) {
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LOG_ERR("Device is registered as slave");
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return -EBUSY;
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}
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#endif
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addr <<= 1;
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for (int i = 0U; i < num_msgs; i++) {
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if ((msgs[i].flags & I2C_MSG_RW_MASK) == I2C_MSG_WRITE) {
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ret = i2c_xec_poll_write(dev, msgs[i], addr);
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if (ret) {
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LOG_ERR("Write error: %d", ret);
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return ret;
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}
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} else {
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ret = i2c_xec_poll_read(dev, msgs[i], addr);
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if (ret) {
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LOG_ERR("Read error: %d", ret);
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return ret;
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}
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}
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}
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return 0;
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}
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static void i2c_xec_bus_isr(void *arg)
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{
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#ifdef CONFIG_I2C_SLAVE
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struct device *dev = (struct device *)arg;
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const struct i2c_xec_config *config =
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(const struct i2c_xec_config *const) (dev->config);
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struct i2c_xec_data *data = dev->data;
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const struct i2c_slave_callbacks *slave_cb = data->slave_cfg->callbacks;
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uint32_t ba = config->base_addr;
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uint32_t status;
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uint8_t val;
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uint8_t dummy = 0U;
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if (!data->slave_attached) {
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return;
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}
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/* Get current status */
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status = MCHP_I2C_SMB_STS_RO(ba);
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/* Bus Error */
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if (status & MCHP_I2C_SMB_STS_BER) {
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if (slave_cb->stop) {
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slave_cb->stop(data->slave_cfg);
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}
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restart_slave(ba);
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goto clear_iag;
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}
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/* External stop */
|
|
if (status & MCHP_I2C_SMB_STS_EXT_STOP) {
|
|
if (slave_cb->stop) {
|
|
slave_cb->stop(data->slave_cfg);
|
|
}
|
|
dummy = MCHP_I2C_SMB_DATA(ba);
|
|
restart_slave(ba);
|
|
goto clear_iag;
|
|
}
|
|
|
|
/* Address byte handling */
|
|
if (status & MCHP_I2C_SMB_STS_AAS) {
|
|
uint8_t slv_data = MCHP_I2C_SMB_DATA(ba);
|
|
|
|
if (!(slv_data & BIT(I2C_READ_WRITE_POS))) {
|
|
/* Slave receive */
|
|
data->slave_read = false;
|
|
if (slave_cb->write_requested) {
|
|
slave_cb->write_requested(data->slave_cfg);
|
|
}
|
|
goto clear_iag;
|
|
} else {
|
|
/* Slave transmit */
|
|
data->slave_read = true;
|
|
if (slave_cb->read_requested) {
|
|
slave_cb->read_requested(data->slave_cfg, &val);
|
|
}
|
|
MCHP_I2C_SMB_DATA(ba) = val;
|
|
goto clear_iag;
|
|
}
|
|
}
|
|
|
|
/* Slave transmit */
|
|
if (data->slave_read) {
|
|
/* Master has Nacked, then just write a dummy byte */
|
|
if (MCHP_I2C_SMB_STS_RO(ba) & MCHP_I2C_SMB_STS_LRB_AD0) {
|
|
MCHP_I2C_SMB_DATA(ba) = dummy;
|
|
} else {
|
|
if (slave_cb->read_processed) {
|
|
slave_cb->read_processed(data->slave_cfg, &val);
|
|
}
|
|
MCHP_I2C_SMB_DATA(ba) = val;
|
|
}
|
|
} else {
|
|
val = MCHP_I2C_SMB_DATA(ba);
|
|
/* TODO NACK Master */
|
|
if (slave_cb->write_received) {
|
|
slave_cb->write_received(data->slave_cfg, val);
|
|
}
|
|
}
|
|
|
|
clear_iag:
|
|
MCHP_GIRQ_SRC(config->girq_id) = BIT(config->girq_bit);
|
|
#endif
|
|
}
|
|
|
|
#ifdef CONFIG_I2C_SLAVE
|
|
static int i2c_xec_slave_register(const struct device *dev,
|
|
struct i2c_slave_config *config)
|
|
{
|
|
const struct i2c_xec_config *cfg = dev->config;
|
|
struct i2c_xec_data *data = dev->data;
|
|
uint32_t ba = cfg->base_addr;
|
|
int ret;
|
|
int counter = 0;
|
|
|
|
if (!config) {
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (data->slave_attached) {
|
|
return -EBUSY;
|
|
}
|
|
|
|
/* Wait for any outstanding transactions to complete so that
|
|
* the bus is free
|
|
*/
|
|
while (!(MCHP_I2C_SMB_STS_RO(ba) & MCHP_I2C_SMB_STS_NBB)) {
|
|
ret = xec_spin_yield(&counter);
|
|
|
|
if (ret < 0) {
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
data->slave_cfg = config;
|
|
|
|
/* Set own address */
|
|
MCHP_I2C_SMB_OWN_ADDR(ba) = data->slave_cfg->address;
|
|
restart_slave(ba);
|
|
|
|
data->slave_attached = true;
|
|
|
|
/* Clear before enabling girq bit */
|
|
MCHP_GIRQ_SRC(cfg->girq_id) = BIT(cfg->girq_bit);
|
|
MCHP_GIRQ_ENSET(cfg->girq_id) = BIT(cfg->girq_bit);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int i2c_xec_slave_unregister(const struct device *dev,
|
|
struct i2c_slave_config *config)
|
|
{
|
|
const struct i2c_xec_config *cfg = dev->config;
|
|
struct i2c_xec_data *data = dev->data;
|
|
|
|
if (!data->slave_attached) {
|
|
return -EINVAL;
|
|
}
|
|
|
|
data->slave_attached = false;
|
|
|
|
MCHP_GIRQ_ENCLR(cfg->girq_id) = BIT(cfg->girq_bit);
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
static const struct i2c_driver_api i2c_xec_driver_api = {
|
|
.configure = i2c_xec_configure,
|
|
.transfer = i2c_xec_transfer,
|
|
#ifdef CONFIG_I2C_SLAVE
|
|
.slave_register = i2c_xec_slave_register,
|
|
.slave_unregister = i2c_xec_slave_unregister,
|
|
#endif
|
|
};
|
|
|
|
static int i2c_xec_init(const struct device *dev)
|
|
{
|
|
struct i2c_xec_data *data =
|
|
(struct i2c_xec_data *const) (dev->data);
|
|
int ret;
|
|
|
|
data->pending_stop = 0;
|
|
data->slave_attached = false;
|
|
|
|
/* Default configuration */
|
|
ret = i2c_xec_configure(dev,
|
|
I2C_MODE_MASTER |
|
|
I2C_SPEED_SET(I2C_SPEED_STANDARD));
|
|
if (ret) {
|
|
LOG_ERR("i2c configure failed %d", ret);
|
|
return ret;
|
|
}
|
|
|
|
#ifdef CONFIG_I2C_SLAVE
|
|
const struct i2c_xec_config *config =
|
|
(const struct i2c_xec_config *const) (dev->config);
|
|
|
|
config->irq_config_func();
|
|
#endif
|
|
return 0;
|
|
}
|
|
|
|
#define I2C_XEC_DEVICE(n) \
|
|
static void i2c_xec_irq_config_func_##n(void); \
|
|
\
|
|
static struct i2c_xec_data i2c_xec_data_##n; \
|
|
static const struct i2c_xec_config i2c_xec_config_##n = { \
|
|
.base_addr = \
|
|
DT_INST_REG_ADDR(n), \
|
|
.port_sel = DT_INST_PROP(n, port_sel), \
|
|
.girq_id = DT_INST_PROP(n, girq), \
|
|
.girq_bit = DT_INST_PROP(n, girq_bit), \
|
|
.irq_config_func = i2c_xec_irq_config_func_##n, \
|
|
}; \
|
|
DEVICE_DT_INST_DEFINE(n, &i2c_xec_init, NULL, \
|
|
&i2c_xec_data_##n, &i2c_xec_config_##n, \
|
|
POST_KERNEL, CONFIG_I2C_INIT_PRIORITY, \
|
|
&i2c_xec_driver_api); \
|
|
\
|
|
static void i2c_xec_irq_config_func_##n(void) \
|
|
{ \
|
|
IRQ_CONNECT(DT_INST_IRQN(n), \
|
|
DT_INST_IRQ(n, priority), \
|
|
i2c_xec_bus_isr, \
|
|
DEVICE_DT_INST_GET(n), 0); \
|
|
irq_enable(DT_INST_IRQN(n)); \
|
|
}
|
|
|
|
DT_INST_FOREACH_STATUS_OKAY(I2C_XEC_DEVICE)
|