145 lines
4.0 KiB
ArmAsm
145 lines
4.0 KiB
ArmAsm
/*
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* Copyright (c) 2016 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <kernel_structs.h>
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/* exports */
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GTEXT(__start)
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GTEXT(__reset)
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/* imports */
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GTEXT(_PrepC)
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GTEXT(_interrupt_stack)
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/* Allow use of r1/at (the assembler temporary register) in this
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* code, normally reserved for internal assembler use
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*/
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.set noat
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#if CONFIG_INCLUDE_RESET_VECTOR
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/*
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* Reset vector entry point into the system. Placed into special 'reset'
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* section so that the linker puts this at ALT_CPU_RESET_ADDR defined in
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* system.h
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*
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* This code can be at most 0x20 bytes, since the exception vector for Nios II
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* is usually configured to be 0x20 past the reset vector.
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*/
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SECTION_FUNC(reset, __reset)
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#if ALT_CPU_ICACHE_SIZE > 0
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/* Aside from the instruction cache line associated with the reset
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* vector, the contents of the cache memories are indeterminate after
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* reset. To ensure cache coherency after reset, the reset handler
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* located at the reset vector must immediately initialize the
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* instruction cache. Next, either the reset handler or a subsequent
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* routine should proceed to initialize the data cache.
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*
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* The cache memory sizes are *always* a power of 2.
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*/
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#if ALT_CPU_ICACHE_SIZE > 0x8000
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movhi r2, %hi(ALT_CPU_ICACHE_SIZE)
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#else
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movui r2, ALT_CPU_ICACHE_SIZE
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#endif
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0:
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/* If ECC present, need to execute initd for each word address
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* to ensure ECC parity bits in data RAM get initialized
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*/
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#ifdef ALT_CPU_ECC_PRESENT
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subi r2, r2, 4
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#else
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subi r2, r2, ALT_CPU_ICACHE_LINE_SIZE
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#endif
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initi r2
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bgt r2, zero, 0b
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#endif /* ALT_CPU_ICACHE_SIZE > 0 */
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/* Done all we need to do here, jump to __text_start */
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movhi r1, %hi(__start)
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ori r1, r1, %lo(__start)
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jmp r1
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#endif /* CONFIG_INCLUDE_RESET_VECTOR */
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/* Remainder of asm-land initialization code before we can jump into
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* the C domain
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*/
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SECTION_FUNC(TEXT, __start)
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/* TODO if shadow register sets enabled, ensure we are in set 0
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* GH-1821
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*/
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/* Initialize the data cache if booting from bare metal. If
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* we're not booting from our reset vector, either by a bootloader
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* or JTAG, assume caches already initialized.
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*/
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#if ALT_CPU_DCACHE_SIZE > 0 && defined(CONFIG_INCLUDE_RESET_VECTOR)
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/* Per documentation data cache size is always a power of two. */
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#if ALT_CPU_DCACHE_SIZE > 0x8000
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movhi r2, %hi(ALT_CPU_DCACHE_SIZE)
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#else
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movui r2, ALT_CPU_DCACHE_SIZE
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#endif
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0:
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/* If ECC present, need to execute initd for each word address
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* to ensure ECC parity bits in data RAM get initialized
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*/
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#ifdef ALT_CPU_ECC_PRESENT
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subi r2, r2, 4
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#else
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subi r2, r2, ALT_CPU_DCACHE_LINE_SIZE
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#endif
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initd 0(r2)
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bgt r2, zero, 0b
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#endif /* ALT_CPU_DCACHE_SIZE && defined(CONFIG_INCLUDE_RESET_VECTOR) */
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#ifdef CONFIG_INIT_STACKS
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/* Pre-populate all bytes in _interrupt_stack with 0xAA
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* init.c enforces that the _interrupt_stack pointer
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* and CONFIG_ISR_STACK_SIZE are a multiple of STACK_ALIGN (4) */
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movhi r1, %hi(_interrupt_stack)
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ori r1, r1, %lo(_interrupt_stack)
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movhi r2, %hi(CONFIG_ISR_STACK_SIZE)
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ori r2, r2, %lo(CONFIG_ISR_STACK_SIZE)
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/* Put constant 0xaaaaaaaa in r3 */
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movhi r3, 0xaaaa
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ori r3, r3, 0xaaaa
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1:
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/* Loop through the _interrupt_stack treating it as an array of
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* u32_t, setting each element to r3 */
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stw r3, (r1)
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subi r2, r2, 4
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addi r1, r1, 4
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blt r0, r2, 1b
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#endif
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/* Set up the initial stack pointer to the interrupt stack, safe
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* to use this as the CPU boots up with interrupts disabled and we
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* don't turn them on until much later, when the kernel is on
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* the main stack */
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movhi sp, %hi(_interrupt_stack)
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ori sp, sp, %lo(_interrupt_stack)
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addi sp, sp, CONFIG_ISR_STACK_SIZE
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#if defined(CONFIG_GP_LOCAL) || defined(CONFIG_GP_GLOBAL) || \
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defined(CONFIG_GP_ALL_DATA)
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/* Initialize global pointer with the linker variable we set */
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movhi gp, %hi(_gp)
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ori gp, gp, %lo(_gp)
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#endif
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/* TODO if shadow register sets enabled, interate through them to set
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* up. Need to clear r0, write gp, set the exception stack pointer
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* GH-1821
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*/
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/* Jump into C domain. _PrepC zeroes BSS, copies rw data into RAM,
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* and then enters z_cstart */
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call _PrepC
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