Leandro Pereira edd18c8f5a arch: x86: Better document that CR0.WP will also be set when CR0.PG is ... Setting bit CR0.WP (bit 16) will inhibit supervisor threads from writing to RO pages. It's a necessary flag to be set, and the constant name CR0_PAGING_ENABLE didn't reflect the fact that the 16th bit was being set. Signed-off-by: Leandro Pereira <leandro.pereira@intel.com>		2018-05-26 19:09:33 -04:00
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offsets	debug: remove DEBUG_INFO option	2018-02-12 13:58:28 -08:00
CMakeLists.txt	arch: x86: Allow disabling speculative store bypass	2018-05-24 13:07:12 -04:00
Kconfig	arch: x86: Allow disabling speculative store bypass	2018-05-24 13:07:12 -04:00
cache.c	…
cache_s.S	…
cpuhalt.c	tests: benchmark: boot_time: Reading time stamps made arch agnostic	2017-06-16 07:37:37 -05:00
crt0.S	arch: x86: Better document that CR0.WP will also be set when CR0.PG is	2018-05-26 19:09:33 -04:00
excstub.S	arch: x86: Use retpolines in core assembly routines	2018-04-24 04:00:01 +05:30
fatal.c	arch: x86: Unwind the stack on fatal errors	2018-03-16 14:12:15 -07:00
float.c	…
intstub.S	kernel: Remove legacy preemption checking	2018-05-25 09:40:55 -07:00
irq_manage.c	kernel: Remove legacy preemption checking	2018-05-25 09:40:55 -07:00
irq_offload.c	…
reboot_rst_cnt.c	…
spec_ctrl.c	arch: x86: Allow disabling speculative store bypass	2018-05-24 13:07:12 -04:00
swap.S	arch: x86: Use retpolines in core assembly routines	2018-04-24 04:00:01 +05:30
sys_fatal_error_handler.c	qemu_x86: terminate emulator on fatal system error	2017-07-22 09:46:26 -04:00
thread.c	x86: fix logic for thread wrappers	2018-03-16 14:12:15 -07:00
userspace.S	arch: x86: Use retpolines in core assembly routines	2018-04-24 04:00:01 +05:30
x86_mmu.c	newlib: fix heap user mode access for MPU devices	2018-05-10 15:09:02 -07:00