zephyr

History

Gil Pitney 9d2f370ddb boards: cc3220sf_launchxl: Make cc3220sf XIP by default Previously, there was no easy command-line solution for loading a Zephyr program to (internal) flash. So, the default development method was to load via gdb/openocd to SRAM and debug from there, thus making the cc3220sf platform non-XIP (CONFIG_XIP=n) by default. With new openocd v 1.10 updates from TI (git.ti.com/sdo-emu), the image can now be flashed and debugged via gdb/openocd, so the default will be changed to XIP (CONFIG_XIP=y). Signed-off-by: Gil Pitney <gil.pitney@linaro.org>		2018-05-25 11:59:00 -05:00
..
CMakeLists.txt	…
Kconfig.defconfig.cc3220sf	boards: cc3220sf_launchxl: Make cc3220sf XIP by default	2018-05-25 11:59:00 -05:00
Kconfig.defconfig.series	kconfig: Make 'source' non-globbing and use 'gsource'	2018-05-08 11:14:12 +02:00
Kconfig.series	arch: arm: Refactor CONFIG_CORTEX_M	2018-03-10 11:42:25 -06:00
Kconfig.soc	…
README	…
dts.fixup	scripts: extract_dts_includes: Generate'_0' defines only when needed	2018-05-10 10:38:23 -05:00
linker.ld	…
soc.c	cc3220sf: soc: Update PRCM call to allow use of ROM API	2018-05-08 17:35:25 -05:00
soc.h	soc: ti_simplelink: cc32xx: Remove ARMV7_M guard from CMSIS_IRQn_Type	2018-02-06 17:34:25 -06:00

README

CC3220 Info taken from:
* http://www.ti.com/lit/ug/swru465/swru465.pdf

Notes for CC3220SF:
 * Text must start at 0x800 offset in flash.  The first 0x800 bytes are
   reserved for the flash header.
 * See CONFIG_TEXT_SECTION_OFFSET.