200 lines
5.3 KiB
C
200 lines
5.3 KiB
C
/*
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* Copyright (c) 2014-2015 Wind River Systems, Inc.
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* Copyright (c) 2016, Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief System/hardware module for fsl_frdm_k64f platform
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*
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* This module provides routines to initialize and support board-level
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* hardware for the fsl_frdm_k64f platform.
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*/
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#include <kernel.h>
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#include <device.h>
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#include <init.h>
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#include <soc.h>
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#include <uart.h>
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#include <linker/sections.h>
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#include <fsl_common.h>
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#include <fsl_clock.h>
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#include <arch/cpu.h>
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#include <cortex_m/exc.h>
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#define PLLFLLSEL_MCGFLLCLK (0)
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#define PLLFLLSEL_MCGPLLCLK (1)
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#define PLLFLLSEL_IRC48MHZ (3)
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#define ER32KSEL_OSC32KCLK (0)
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#define ER32KSEL_RTC (2)
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#define ER32KSEL_LPO1KHZ (3)
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#define TIMESRC_OSCERCLK (2)
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/*
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* K64F Flash configuration fields
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* These 16 bytes, which must be loaded to address 0x400, include default
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* protection and security settings.
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* They are loaded at reset to various Flash Memory module (FTFE) registers.
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*
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* The structure is:
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* -Backdoor Comparison Key for unsecuring the MCU - 8 bytes
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* -Program flash protection bytes, 4 bytes, written to FPROT0-3
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* -Flash security byte, 1 byte, written to FSEC
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* -Flash nonvolatile option byte, 1 byte, written to FOPT
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* -Reserved, 1 byte, (Data flash protection byte for FlexNVM)
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* -Reserved, 1 byte, (EEPROM protection byte for FlexNVM)
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*
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*/
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u8_t __kinetis_flash_config_section __kinetis_flash_config[] = {
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/* Backdoor Comparison Key (unused) */
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0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
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/* Program flash protection; 1 bit/region - 0=protected, 1=unprotected
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*/
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0xFF, 0xFF, 0xFF, 0xFF,
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/*
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* Flash security: Backdoor key disabled, Mass erase enabled,
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* Factory access enabled, MCU is unsecure
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*/
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0xFE,
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/* Flash nonvolatile option: NMI enabled, EzPort enabled, Normal boot */
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0xFF,
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/* Reserved for FlexNVM feature (unsupported by this MCU) */
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0xFF, 0xFF};
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static const osc_config_t oscConfig = {
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.freq = CONFIG_OSC_XTAL0_FREQ,
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.capLoad = 0,
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#if defined(CONFIG_OSC_EXTERNAL)
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.workMode = kOSC_ModeExt,
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#elif defined(CONFIG_OSC_LOW_POWER)
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.workMode = kOSC_ModeOscLowPower,
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#elif defined(CONFIG_OSC_HIGH_GAIN)
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.workMode = kOSC_ModeOscHighGain,
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#else
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#error "An oscillator mode must be defined"
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#endif
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.oscerConfig = {
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.enableMode = kOSC_ErClkEnable,
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#if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && \
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FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER)
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.erclkDiv = 0U,
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#endif
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},
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};
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static const mcg_pll_config_t pll0Config = {
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.enableMode = 0U,
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.prdiv = CONFIG_MCG_PRDIV0,
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.vdiv = CONFIG_MCG_VDIV0,
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};
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static const sim_clock_config_t simConfig = {
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.pllFllSel = PLLFLLSEL_MCGPLLCLK, /* PLLFLLSEL select PLL. */
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.er32kSrc = ER32KSEL_RTC, /* ERCLK32K selection, use RTC. */
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.clkdiv1 = SIM_CLKDIV1_OUTDIV1(CONFIG_K64_CORE_CLOCK_DIVIDER - 1) |
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SIM_CLKDIV1_OUTDIV2(CONFIG_K64_BUS_CLOCK_DIVIDER - 1) |
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SIM_CLKDIV1_OUTDIV3(CONFIG_K64_FLEXBUS_CLOCK_DIVIDER - 1) |
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SIM_CLKDIV1_OUTDIV4(CONFIG_K64_FLASH_CLOCK_DIVIDER - 1),
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};
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/**
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*
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* @brief Initialize the system clock
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*
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* This routine will configure the multipurpose clock generator (MCG) to
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* set up the system clock.
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* The MCG has nine possible modes, including Stop mode. This routine assumes
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* that the current MCG mode is FLL Engaged Internal (FEI), as from reset.
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* It transitions through the FLL Bypassed External (FBE) and
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* PLL Bypassed External (PBE) modes to get to the desired
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* PLL Engaged External (PEE) mode and generate the maximum 120 MHz system
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* clock.
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*
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* @return N/A
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*
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*/
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static ALWAYS_INLINE void clkInit(void)
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{
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CLOCK_SetSimSafeDivs();
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CLOCK_InitOsc0(&oscConfig);
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CLOCK_SetXtal0Freq(CONFIG_OSC_XTAL0_FREQ);
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CLOCK_BootToPeeMode(kMCG_OscselOsc, kMCG_PllClkSelPll0, &pll0Config);
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CLOCK_SetInternalRefClkConfig(kMCG_IrclkEnable, kMCG_IrcSlow,
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CONFIG_MCG_FCRDIV);
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CLOCK_SetSimConfig(&simConfig);
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#if CONFIG_ETH_MCUX
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CLOCK_SetEnetTime0Clock(TIMESRC_OSCERCLK);
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#endif
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#if CONFIG_USB_KINETIS
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CLOCK_EnableUsbfs0Clock(kCLOCK_UsbSrcPll0,
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CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC);
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#endif
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}
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/**
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*
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* @brief Perform basic hardware initialization
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*
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* Initialize the interrupt controller device drivers.
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* Also initialize the timer device driver, if required.
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*
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* @return 0
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*/
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static int fsl_frdm_k64f_init(struct device *arg)
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{
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ARG_UNUSED(arg);
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int oldLevel; /* old interrupt lock level */
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#if !defined(CONFIG_HAS_SYSMPU)
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u32_t temp_reg;
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#endif /* !CONFIG_HAS_SYSMPU */
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/* disable interrupts */
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oldLevel = irq_lock();
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/* release I/O power hold to allow normal run state */
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PMC->REGSC |= PMC_REGSC_ACKISO_MASK;
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#if !defined(CONFIG_HAS_SYSMPU)
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/*
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* Disable memory protection and clear slave port errors.
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* Note that the K64F does not implement the optional ARMv7-M memory
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* protection unit (MPU), specified by the architecture (PMSAv7), in the
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* Cortex-M4 core. Instead, the processor includes its own MPU module.
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*/
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temp_reg = SYSMPU->CESR;
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temp_reg &= ~SYSMPU_CESR_VLD_MASK;
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temp_reg |= SYSMPU_CESR_SPERR_MASK;
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SYSMPU->CESR = temp_reg;
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#endif /* !CONFIG_HAS_SYSMPU */
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_ClearFaults();
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/* Initialize PLL/system clock to 120 MHz */
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clkInit();
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/*
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* install default handler that simply resets the CPU
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* if configured in the kernel, NOP otherwise
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*/
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NMI_INIT();
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/* restore interrupt state */
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irq_unlock(oldLevel);
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return 0;
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}
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SYS_INIT(fsl_frdm_k64f_init, PRE_KERNEL_1, 0);
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