d0fe965b9f
Microchip MEC172x has a modified eSPI SAF hardware implementation. Hardware changes include multiple clock dividers for each SPI flash device and data transfer using QMSPI local DMA. espi reset interrupt is made a higer priority in MEC172x devicetree because espi reset event resets all espi hardware and we don't to want to service any other espi interrupt blocks when espi reset occurs. Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com> |
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espi-controller.yaml | ||
microchip,xec-espi-host-dev.yaml | ||
microchip,xec-espi-saf-v2.yaml | ||
microchip,xec-espi-saf.yaml | ||
microchip,xec-espi-v2.yaml | ||
microchip,xec-espi-vw-routing.yaml | ||
microchip,xec-espi.yaml | ||
nuvoton,npcx-espi-vw-conf.yaml | ||
nuvoton,npcx-espi.yaml | ||
nuvoton,npcx-host-sub.yaml | ||
nuvoton,npcx-host-uart.yaml | ||
zephyr,espi-emul-controller.yaml |