42 lines
1.1 KiB
YAML
42 lines
1.1 KiB
YAML
# Copyright (c) 2022 STMicroelectronics
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# SPDX-License-Identifier: Apache-2.0
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description: |
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STM32 HSI Clock node description for STM32G0 devices
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On STM32G0, HSI is a 16MHz fixed clock.
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It also produces a HSISYS secondary clk which can be used as system clock
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source. In that case, a HSI divisor (ranges from 1 to 128) can be applied:
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SYSCLK = HSI16 / HSI DIV
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enum:
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- 1 ==> HSISYS = 16MHZ
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- 2 ==> HSISYS = 8MHZ
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- 4 ==> HSISYS = 4MHZ
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- 8 ==> HSISYS = 2MHZ
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- 16 ==> HSISYS = 1MHZ
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- 32 ==> HSISYS = 0.5MHz
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- 64 ==> HSISYS = 0.25MHZ
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- 128 ==> HSISYS = 0.125MHz
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compatible: "st,stm32g0-hsi-clock"
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include: [fixed-clock.yaml]
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properties:
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hsi-div:
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type: int
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required: true
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description: |
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HSI clock divider. Configures the output HSI clock frequency (HSISYS),
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It does not apply to HSI clk selected as peripheral source clock
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(eg: RNG clk driven by HSI)
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enum:
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- 1
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- 2
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- 4
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- 8
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- 16
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- 32
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- 64
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- 128
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