37 lines
1012 B
YAML
37 lines
1012 B
YAML
# Copyright (c) 2021, Linaro ltd
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# SPDX-License-Identifier: Apache-2.0
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description: |
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Main PLL node binding for STM32F100 devices
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Takes one of clk_hse or clk_hsi as input clock.
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When clk_hsi is used a fixed prescaler is applied. When input clock is hse or
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pll2, configurable prescaler is used.
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Up to 2 output clocks could be supported and for each output clock, the
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frequency can be computed with the following formula:
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f(PLLCLK) = f(PLLIN) x PLLMUL --> SYSCLK (System Clock)
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with, depending on the case:
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f(PLLIN) = f(input_clk) / 2 if input_clk = clk_hsi
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f(PLLIN) = f(input_clk) / PREDIV if input_clk = clk_hse
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The PLL output frequency must not exceed 24 MHz.
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compatible: "st,stm32f100-pll-clock"
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include:
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- name: st,stm32f105-pll-clock.yaml
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property-blocklist:
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- mul
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properties:
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mul:
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type: int
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required: true
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description: |
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PLL multiplication factor for output clock
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Valid range: 2 - 16
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