48 lines
1.1 KiB
YAML
48 lines
1.1 KiB
YAML
# Copyright (c) 2021, Linaro ltd
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# SPDX-License-Identifier: Apache-2.0
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description: |
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Main PLL node binding for low-, medium-, high- and XL-density STM32F1 devices.
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Takes one of 'clk_hse', 'clk_hse / 2' (when 'xtpre' is set) or 'clk_hsi / 2'
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as input clock.
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Up to 2 output clocks could be supported and for each output clock, the
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frequency can be computed with the following formula:
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f(PLLCLK) = f(input clk) x PLLMUL --> SYSCLK (System Clock)
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f(USBCLK) = f(PLLCLK) / USBPRE --> USB
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The PLL output frequency must not exceed 72 MHz.
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compatible: "st,stm32f1-pll-clock"
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include: [clock-controller.yaml, base.yaml]
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properties:
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"#clock-cells":
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const: 0
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clocks:
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required: true
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mul:
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type: int
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required: true
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description: |
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Main PLL multiplication factor for VCO
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Valid range: 2 - 16
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xtpre:
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type: boolean
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required: false
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description: |
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Otpional HSE divider for PLL entry
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usbpre:
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type: int
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required: false
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description: |
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Otpional HSE divider for PLL entry
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