50 lines
1.0 KiB
YAML
50 lines
1.0 KiB
YAML
# Copyright (c) 2021, Microchip Technology Inc.
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# SPDX-License-Identifier: Apache-2.0
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description: Microchip XEC Power Clock Reset and VBAT register (PCR)
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compatible: "microchip,xec-pcr"
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include: [clock-controller.yaml, base.yaml]
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properties:
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reg:
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required: true
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interrupts:
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required: true
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core-clock-div:
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type: int
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required: true
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description: Divide 96 MHz PLL clock to produce Cortex-M4 core clock
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slow-clock-div:
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type: int
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required: false
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description: |
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PWM and TACH clock domain divided down from 48 MHz AHB clock. The
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default value is 480 for 100 kHz.
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pll-32k-src:
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type: int
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required: true
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description: 32 KHz clock source for PLL
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periph-32k-src:
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type: int
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required: true
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description: 32 KHz clock source for peripherals
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xtal-single-ended:
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type: boolean
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required: false
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description: Use single ended crystal connection to XTAL2 pin.
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"#clock-cells":
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const: 2
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clock-cells:
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- regidx
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- bitpos
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