349 lines
8.6 KiB
C
349 lines
8.6 KiB
C
/* gpio_sch.c - Driver implementation for Intel SCH GPIO controller */
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/*
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* Copyright (c) 2015 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <errno.h>
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#include <kernel.h>
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#include <board.h>
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#include <init.h>
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#include <sys_io.h>
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#include <misc/util.h>
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#include "gpio_sch.h"
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#include "gpio_utils.h"
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#define SYS_LOG_LEVEL CONFIG_SYS_LOG_GPIO_LEVEL
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#include <logging/sys_log.h>
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/* Define GPIO_SCH_LEGACY_IO_PORTS_ACCESS
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* inside soc.h if the GPIO controller
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* requires I/O port access instead of
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* memory mapped I/O.
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*/
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#ifdef GPIO_SCH_LEGACY_IO_PORTS_ACCESS
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#define _REG_READ sys_in32
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#define _REG_WRITE sys_out32
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#define _REG_SET_BIT sys_io_set_bit
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#define _REG_CLEAR_BIT sys_io_clear_bit
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#else
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#define _REG_READ sys_read32
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#define _REG_WRITE sys_write32
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#define _REG_SET_BIT sys_set_bit
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#define _REG_CLEAR_BIT sys_clear_bit
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#endif /* GPIO_SCH_LEGACY_IO_PORTS_ACCESS */
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#define DEFINE_MM_REG_READ(__reg, __off) \
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static inline uint32_t _read_##__reg(uint32_t addr) \
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{ \
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return _REG_READ(addr + __off); \
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}
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#define DEFINE_MM_REG_WRITE(__reg, __off) \
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static inline void _write_##__reg(uint32_t data, uint32_t addr) \
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{ \
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_REG_WRITE(data, addr + __off); \
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}
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DEFINE_MM_REG_READ(glvl, GPIO_SCH_REG_GLVL)
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DEFINE_MM_REG_WRITE(glvl, GPIO_SCH_REG_GLVL)
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DEFINE_MM_REG_WRITE(gtpe, GPIO_SCH_REG_GTPE)
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DEFINE_MM_REG_WRITE(gtne, GPIO_SCH_REG_GTNE)
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DEFINE_MM_REG_READ(gts, GPIO_SCH_REG_GTS)
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DEFINE_MM_REG_WRITE(gts, GPIO_SCH_REG_GTS)
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static void _set_bit(uint32_t base_addr,
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uint32_t bit, uint8_t set)
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{
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if (!set) {
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_REG_CLEAR_BIT(base_addr, bit);
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} else {
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_REG_SET_BIT(base_addr, bit);
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}
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}
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#define DEFINE_MM_REG_SET_BIT(__reg, __off) \
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static inline void _set_bit_##__reg(uint32_t addr, \
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uint32_t bit, uint8_t set) \
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{ \
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_set_bit(addr + __off, bit, set); \
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}
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DEFINE_MM_REG_SET_BIT(gen, GPIO_SCH_REG_GEN)
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DEFINE_MM_REG_SET_BIT(gio, GPIO_SCH_REG_GIO)
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DEFINE_MM_REG_SET_BIT(glvl, GPIO_SCH_REG_GLVL)
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DEFINE_MM_REG_SET_BIT(gtpe, GPIO_SCH_REG_GTPE)
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DEFINE_MM_REG_SET_BIT(gtne, GPIO_SCH_REG_GTNE)
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static inline void _set_data_reg(uint32_t *reg, uint8_t pin, uint8_t set)
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{
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*reg &= ~(BIT(pin));
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*reg |= (set << pin) & BIT(pin);
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}
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static void _gpio_pin_config(struct device *dev, uint32_t pin, int flags)
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{
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const struct gpio_sch_config *info = dev->config->config_info;
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struct gpio_sch_data *gpio = dev->driver_data;
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uint8_t active_high = 0;
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uint8_t active_low = 0;
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_set_bit_gen(info->regs, pin, 1);
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_set_bit_gio(info->regs, pin, !(flags & GPIO_DIR_MASK));
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if (flags & GPIO_INT) {
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if (flags & GPIO_INT_ACTIVE_HIGH) {
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active_high = 1;
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} else {
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active_low = 1;
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}
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SYS_LOG_DBG("Setting up pin %d to active_high %d and "
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"active_low %d", active_high, active_low);
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}
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/* We store the gtpe/gtne settings. These will be used once
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* we enable the callback for the pin, or the whole port
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*/
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_set_data_reg(&gpio->int_regs.gtpe, pin, active_high);
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_set_data_reg(&gpio->int_regs.gtne, pin, active_low);
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}
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static inline void _gpio_port_config(struct device *dev, int flags)
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{
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const struct gpio_sch_config *info = dev->config->config_info;
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int pin;
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for (pin = 0; pin < info->bits; pin++) {
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_gpio_pin_config(dev, pin, flags);
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}
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}
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static int gpio_sch_config(struct device *dev,
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int access_op, uint32_t pin, int flags)
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{
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const struct gpio_sch_config *info = dev->config->config_info;
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if (access_op == GPIO_ACCESS_BY_PIN) {
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if (pin >= info->bits) {
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return -EINVAL;
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}
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_gpio_pin_config(dev, pin, flags);
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} else {
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_gpio_port_config(dev, flags);
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}
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return 0;
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}
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static int gpio_sch_write(struct device *dev,
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int access_op, uint32_t pin, uint32_t value)
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{
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const struct gpio_sch_config *info = dev->config->config_info;
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if (access_op == GPIO_ACCESS_BY_PIN) {
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if (pin >= info->bits) {
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return -ENOTSUP;
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}
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_set_bit_glvl(info->regs, pin, value);
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} else {
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_write_glvl(info->regs, value);
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}
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return 0;
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}
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static int gpio_sch_read(struct device *dev,
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int access_op, uint32_t pin, uint32_t *value)
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{
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const struct gpio_sch_config *info = dev->config->config_info;
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*value = _read_glvl(info->regs);
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if (access_op == GPIO_ACCESS_BY_PIN) {
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if (pin >= info->bits) {
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return -ENOTSUP;
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}
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*value = !!(*value & BIT(pin));
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}
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return 0;
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}
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static void _gpio_sch_poll_status(void *arg1, void *unused1, void *unused2)
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{
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struct device *dev = (struct device *)arg1;
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const struct gpio_sch_config *info = dev->config->config_info;
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struct gpio_sch_data *gpio = dev->driver_data;
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ARG_UNUSED(unused1);
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ARG_UNUSED(unused2);
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/* Cleaning up GTS first */
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_write_gts(_read_gts(info->regs), info->regs);
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while (gpio->poll) {
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uint32_t status;
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status = _read_gts(info->regs);
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if (!status) {
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goto loop;
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}
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_gpio_fire_callbacks(&gpio->callbacks, dev, status);
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/* It's not documented but writing the same status value
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* into GTS tells to the controller it got handled.
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*/
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_write_gts(status, info->regs);
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loop:
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k_timer_start(&gpio->poll_timer, GPIO_SCH_POLLING_MSEC, 0);
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k_timer_status_sync(&gpio->poll_timer);
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}
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}
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static void _gpio_sch_manage_callback(struct device *dev)
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{
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struct gpio_sch_data *gpio = dev->driver_data;
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/* Start the fiber only when relevant */
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if (!sys_slist_is_empty(&gpio->callbacks) && gpio->cb_enabled) {
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if (!gpio->poll) {
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SYS_LOG_DBG("Starting SCH GPIO polling fiber");
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gpio->poll = 1;
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k_thread_spawn(gpio->polling_stack,
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GPIO_SCH_POLLING_STACK_SIZE,
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(k_thread_entry_t)_gpio_sch_poll_status,
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dev, NULL, NULL,
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K_PRIO_COOP(1), 0, 0);
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}
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} else {
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gpio->poll = 0;
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}
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}
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static int gpio_sch_manage_callback(struct device *dev,
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struct gpio_callback *callback, bool set)
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{
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struct gpio_sch_data *gpio = dev->driver_data;
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_gpio_manage_callback(&gpio->callbacks, callback, set);
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_gpio_sch_manage_callback(dev);
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return 0;
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}
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static int gpio_sch_enable_callback(struct device *dev,
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int access_op, uint32_t pin)
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{
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const struct gpio_sch_config *info = dev->config->config_info;
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struct gpio_sch_data *gpio = dev->driver_data;
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if (access_op == GPIO_ACCESS_BY_PIN) {
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uint32_t bits = BIT(pin);
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if (pin >= info->bits) {
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return -ENOTSUP;
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}
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_set_bit_gtpe(info->regs, pin, !!(bits & gpio->int_regs.gtpe));
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_set_bit_gtne(info->regs, pin, !!(bits & gpio->int_regs.gtne));
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gpio->cb_enabled |= bits;
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} else {
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_write_gtpe(gpio->int_regs.gtpe, info->regs);
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_write_gtne(gpio->int_regs.gtne, info->regs);
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gpio->cb_enabled = BIT_MASK(info->bits);
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}
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_gpio_sch_manage_callback(dev);
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return 0;
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}
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static int gpio_sch_disable_callback(struct device *dev,
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int access_op, uint32_t pin)
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{
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const struct gpio_sch_config *info = dev->config->config_info;
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struct gpio_sch_data *gpio = dev->driver_data;
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if (access_op == GPIO_ACCESS_BY_PIN) {
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if (pin >= info->bits) {
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return -ENOTSUP;
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}
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_set_bit_gtpe(info->regs, pin, 0);
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_set_bit_gtne(info->regs, pin, 0);
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gpio->cb_enabled &= ~BIT(pin);
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} else {
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_write_gtpe(0, info->regs);
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_write_gtne(0, info->regs);
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gpio->cb_enabled = 0;
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}
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_gpio_sch_manage_callback(dev);
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return 0;
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}
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static const struct gpio_driver_api gpio_sch_api = {
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.config = gpio_sch_config,
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.write = gpio_sch_write,
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.read = gpio_sch_read,
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.manage_callback = gpio_sch_manage_callback,
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.enable_callback = gpio_sch_enable_callback,
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.disable_callback = gpio_sch_disable_callback,
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};
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static int gpio_sch_init(struct device *dev)
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{
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struct gpio_sch_data *gpio = dev->driver_data;
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dev->driver_api = &gpio_sch_api;
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k_timer_init(&gpio->poll_timer, NULL, NULL);
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SYS_LOG_DBG("SCH GPIO Intel Driver initialized on device: %p", dev);
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return 0;
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}
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#if CONFIG_GPIO_SCH_0
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static const struct gpio_sch_config gpio_sch_0_config = {
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.regs = GPIO_SCH_0_BASE_ADDR,
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.bits = GPIO_SCH_0_BITS,
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};
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static struct gpio_sch_data gpio_data_0;
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DEVICE_INIT(gpio_0, CONFIG_GPIO_SCH_0_DEV_NAME, gpio_sch_init,
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&gpio_data_0, &gpio_sch_0_config,
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POST_KERNEL, CONFIG_GPIO_SCH_INIT_PRIORITY);
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#endif /* CONFIG_GPIO_SCH_0 */
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#if CONFIG_GPIO_SCH_1
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static const struct gpio_sch_config gpio_sch_1_config = {
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.regs = GPIO_SCH_1_BASE_ADDR,
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.bits = GPIO_SCH_1_BITS,
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};
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static struct gpio_sch_data gpio_data_1;
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DEVICE_INIT(gpio_1, CONFIG_GPIO_SCH_1_DEV_NAME, gpio_sch_init,
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&gpio_data_1, &gpio_sch_1_config,
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POST_KERNEL, CONFIG_GPIO_SCH_INIT_PRIORITY);
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#endif /* CONFIG_GPIO_SCH_1 */
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