331 lines
7.9 KiB
Plaintext
331 lines
7.9 KiB
Plaintext
/*
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* Copyright (c) 2019 STMicroelectronics
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* Copyright (c) 2019 Centaur Analytics, Inc
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <freq.h>
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#include <arm/armv7-m.dtsi>
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <zephyr/dt-bindings/clock/stm32_clock.h>
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#include <zephyr/dt-bindings/i2c/i2c.h>
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#include <zephyr/dt-bindings/pwm/pwm.h>
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#include <zephyr/dt-bindings/pwm/stm32_pwm.h>
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#include <zephyr/dt-bindings/display/stm32_ltdc.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m4";
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reg = <0>;
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};
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};
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retram: memory0@0 {
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compatible = "mmio-sram";
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reg = <0x00000000 DT_SIZE_K(64)>;
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};
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mcusram: memory1@10000000 {
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compatible = "mmio-sram";
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reg = <0x10000000 DT_SIZE_K(320)>;
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};
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soc {
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rcc: rcc@50000000 {
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compatible = "st,stm32mp1-rcc";
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reg = <0x50000000 0x1000>;
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#clock-cells = <2>;
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};
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exti: interrupt-controller@5000d000 {
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compatible = "st,stm32-exti";
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x5000d000 0x400>;
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};
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pinctrl: pin-controller@50002000 {
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compatible = "st,stm32-pinctrl";
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reg = <0x50002000 0x9000>;
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#address-cells = <1>;
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#size-cells = <1>;
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gpioa: gpio@50002000 {
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compatible = "st,stm32-gpio";
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reg = <0x50002000 0x400>;
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gpio-controller;
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#gpio-cells = <2>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000001>;
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};
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gpiob: gpio@50003000 {
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compatible = "st,stm32-gpio";
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reg = <0x50003000 0x400>;
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gpio-controller;
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#gpio-cells = <2>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000002>;
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};
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gpioc: gpio@50004000 {
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compatible = "st,stm32-gpio";
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reg = <0x50004000 0x400>;
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gpio-controller;
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#gpio-cells = <2>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000004>;
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};
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gpiod: gpio@50005000 {
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compatible = "st,stm32-gpio";
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reg = <0x50005000 0x400>;
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gpio-controller;
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#gpio-cells = <2>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000008>;
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};
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gpioe: gpio@50006000 {
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compatible = "st,stm32-gpio";
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reg = <0x50006000 0x400>;
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gpio-controller;
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#gpio-cells = <2>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000010>;
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};
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gpiof: gpio@50007000 {
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compatible = "st,stm32-gpio";
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reg = <0x50007000 0x400>;
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gpio-controller;
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#gpio-cells = <2>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000020>;
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};
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gpiog: gpio@50008000 {
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compatible = "st,stm32-gpio";
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reg = <0x50008000 0x400>;
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gpio-controller;
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#gpio-cells = <2>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000040>;
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};
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gpioh: gpio@50009000 {
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compatible = "st,stm32-gpio";
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reg = <0x50009000 0x400>;
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gpio-controller;
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#gpio-cells = <2>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000080>;
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};
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gpioi: gpio@5000a000 {
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compatible = "st,stm32-gpio";
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reg = <0x5000a000 0x400>;
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gpio-controller;
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#gpio-cells = <2>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000100>;
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};
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gpioj: gpio@5000b000 {
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compatible = "st,stm32-gpio";
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reg = <0x5000b000 0x400>;
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gpio-controller;
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#gpio-cells = <2>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000200>;
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};
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gpiok: gpio@5000c000 {
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compatible = "st,stm32-gpio";
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reg = <0x5000c000 0x400>;
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gpio-controller;
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#gpio-cells = <2>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000400>;
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};
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};
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wwdg: wwdg1: watchdog@4000a000 {
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compatible = "st,stm32-window-watchdog";
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reg = <0x4000a000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
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interrupts = <0 7>;
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status = "disabled";
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};
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dma1: dma@48000000 {
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compatible = "st,stm32-dma-v1";
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#dma-cells = <4>;
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reg = <0x48000000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x1>;
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interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0 47 0>;
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dma-offset = <0>;
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dma-requests = <8>;
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status = "disabled";
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};
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dma2: dma@48001000 {
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compatible = "st,stm32-dma-v1";
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#dma-cells = <4>;
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reg = <0x48001000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x2>;
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interrupts = <56 0 57 0 58 0 59 0 60 0 68 0 69 0 70 0>;
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dma-offset = <8>;
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dma-requests = <8>;
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status = "disabled";
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};
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dmamux: dmamux@48002000 {
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compatible = "st,stm32-dmamux";
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#dma-cells = <3>;
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reg = <0x48002000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x4>;
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interrupts = <102 0>;
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dma-channels = <16>;
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dma-generators = <8>;
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dma-requests= <108>;
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status = "disabled";
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};
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spi1: spi@44004000 {
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compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
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reg = <0x44004000 0x400>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x100>;
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interrupts = <35 5>;
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status = "disabled";
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};
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spi2: spi@4000b000 {
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compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
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reg = <0x4000b000 0x400>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x800>;
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interrupts = <36 5>;
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status = "disabled";
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};
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spi3: spi@4000c000 {
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compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
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reg = <0x4000c000 0x400>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x1000>;
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interrupts = <51 5>;
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status = "disabled";
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};
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spi4: spi@44005000 {
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compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
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reg = <0x44005000 0x400>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x200>;
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interrupts = <84 5>;
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status = "disabled";
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};
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spi5: spi@44009000 {
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compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
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reg = <0x44009000 0x400>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x400>;
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interrupts = <85 5>;
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status = "disabled";
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};
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usart2: serial@4000e000 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x4000e000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
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interrupts = <38 0>;
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status = "disabled";
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};
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usart3: serial@4000f000 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x4000f000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
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interrupts = <39 0>;
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status = "disabled";
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};
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uart4: serial@40010000 {
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compatible = "st,stm32-uart";
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reg = <0x40010000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00010000>;
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interrupts = <52 0>;
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status = "disabled";
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};
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uart5: serial@40011000 {
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compatible = "st,stm32-uart";
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reg = <0x40011000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
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interrupts = <53 0>;
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status = "disabled";
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};
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usart6: serial@44003000 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x44003000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>;
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interrupts = <71 0>;
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status = "disabled";
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};
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uart7: serial@40018000 {
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compatible = "st,stm32-uart";
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reg = <0x40018000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
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interrupts = <82 0>;
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status = "disabled";
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};
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uart8: serial@40019000 {
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compatible = "st,stm32-uart";
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reg = <0x40019000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
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interrupts = <83 0>;
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status = "disabled";
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};
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i2c5: i2c@40015000 {
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compatible = "st,stm32-i2c-v2";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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reg = <0x40015000 0x400>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x01000000>;
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interrupt-names = "event", "error";
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interrupts = <107 0>, <108 0>;
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status = "disabled";
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};
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mailbox: mailbox@4c001000 {
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compatible = "st,stm32-ipcc-mailbox";
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reg = <0x4c001000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00001000>;
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interrupts = <103 0>, <104 0>;
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interrupt-names = "rxo", "txf";
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status = "disabled";
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};
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ltdc: display-controller@5a001000 {
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compatible = "st,stm32-ltdc";
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reg = <0x5a001000 0x200>;
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interrupts = <88 0>, <89 0>;
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interrupt-names = "ltdc", "ltdc_er";
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clocks = <&rcc STM32_CLOCK_BUS_APB4 0x00000001>;
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status = "disabled";
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <4>;
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};
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