zephyr/dts/arm/nxp/nxp_s32z27x_rtu0_r52.dtsi

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/*
* Copyright 2022 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <arm/nxp/nxp_s32z27x_r52.dtsi>
/ {
cpus {
/delete-node/ cpu@4;
/delete-node/ cpu@5;
/delete-node/ cpu@6;
/delete-node/ cpu@7;
};
soc {
stm0: stm@76200000 {
compatible = "nxp,s32-sys-timer";
reg = <0x76200000 0x10000>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
status = "disabled";
};
stm1: stm@76210000 {
compatible = "nxp,s32-sys-timer";
reg = <0x76210000 0x10000>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
status = "disabled";
};
stm2: stm@76020000 {
compatible = "nxp,s32-sys-timer";
reg = <0x76020000 0x10000>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
status = "disabled";
};
stm3: stm@76030000 {
compatible = "nxp,s32-sys-timer";
reg = <0x76030000 0x10000>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
status = "disabled";
};
};
};