422 lines
9.2 KiB
Plaintext
422 lines
9.2 KiB
Plaintext
/*
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* Copyright (c) 2019 ML!PA Consulting GmbH
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv7-m.dtsi>
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#include <zephyr/dt-bindings/gpio/gpio.h>
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#include <zephyr/dt-bindings/i2c/i2c.h>
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#include <zephyr/dt-bindings/pwm/pwm.h>
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/ {
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chosen {
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zephyr,flash-controller = &nvmctrl;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m4f";
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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mpu: mpu@e000ed90 {
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compatible = "arm,armv7m-mpu";
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reg = <0xe000ed90 0x40>;
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arm,num-mpu-regions = <8>;
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};
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};
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};
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aliases {
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adc-0 = &adc0;
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adc-1 = &adc1;
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port-a = &porta;
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port-b = &portb;
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port-c = &portc;
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port-d = &portd;
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sercom-0 = &sercom0;
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sercom-1 = &sercom1;
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sercom-2 = &sercom2;
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sercom-3 = &sercom3;
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sercom-4 = &sercom4;
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sercom-5 = &sercom5;
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sercom-6 = &sercom6;
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sercom-7 = &sercom7;
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tc-0 = &tc0;
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tc-2 = &tc2;
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tc-4 = &tc4;
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tc-6 = &tc6;
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tcc-0 = &tcc0;
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tcc-1 = &tcc1;
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tcc-2 = &tcc2;
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tcc-3 = &tcc3;
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tcc-4 = &tcc4;
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watchdog0 = &wdog;
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};
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chosen {
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zephyr,entropy = &trng;
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};
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soc {
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sram0: memory@20000000 {
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compatible = "mmio-sram";
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reg = <0x20000000 0x40000>;
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};
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backup0: memory@47000000 {
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compatible = "mmio-sram";
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reg = <0x47000000 0x2000>;
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};
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id: device_id@8061fc {
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compatible = "atmel,sam0-id";
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reg = <0x008061FC 0x4>,
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<0x00806010 0x4>,
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<0x00806014 0x4>,
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<0x00806018 0x4>;
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};
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mclk: mclk@40000800 {
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compatible = "atmel,samd5x-mclk";
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reg = <0x40000800 0x400>;
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#clock-cells = <2>;
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};
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gclk: gclk@40001c00 {
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compatible = "atmel,samd5x-gclk";
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reg = <0x40001c00 0x400>;
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#clock-cells = <1>;
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};
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nvmctrl: nvmctrl@41004000 {
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compatible = "atmel,sam0-nvmctrl";
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reg = <0x41004000 0x22>;
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interrupts = <29 0>, <30 0>;
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lock-regions = <32>;
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#address-cells = <1>;
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#size-cells = <1>;
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flash0: flash@0 {
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compatible = "soc-nv-flash";
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write-block-size = <8>;
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};
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};
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dmac: dmac@4100a000 {
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compatible = "atmel,sam0-dmac";
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reg = <0x4100A000 0x50>;
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interrupts = <31 0>, <32 0>, <33 0>, <34 0>, <35 0>;
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#dma-cells = <2>;
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};
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eic: eic@40002800 {
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compatible = "atmel,sam0-eic";
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reg = <0x40002800 0x38>;
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interrupts = <12 0>, <13 0>, <14 0>, <15 0>,
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<16 0>, <17 0>, <18 0>, <19 0>,
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<20 0>, <21 0>, <22 0>, <23 0>,
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<24 0>, <25 0>, <26 0>, <27 0>;
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};
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pinmux_a: pinmux@41008000 {
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compatible = "atmel,sam0-pinmux";
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reg = <0x41008000 0x80>;
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};
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pinmux_b: pinmux@41008080 {
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compatible = "atmel,sam0-pinmux";
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reg = <0x41008080 0x80>;
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};
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pinmux_c: pinmux@41008100 {
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compatible = "atmel,sam0-pinmux";
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reg = <0x41008100 0x80>;
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};
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pinmux_d: pinmux@41008180 {
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compatible = "atmel,sam0-pinmux";
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reg = <0x41008180 0x80>;
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};
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wdog: watchdog@40002000 {
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compatible = "atmel,sam0-watchdog";
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reg = <0x40002000 13>;
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interrupts = <10 0>;
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};
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sercom0: sercom@40003000 {
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compatible = "atmel,sam0-sercom";
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reg = <0x40003000 0x40>;
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interrupts = <46 0>, <47 0>, <48 0>, <49 0>;
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status = "disabled";
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clocks = <&gclk 7>, <&mclk 0x14 12>;
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clock-names = "GCLK", "MCLK";
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};
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sercom1: sercom@40003400 {
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compatible = "atmel,sam0-sercom";
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reg = <0x40003400 0x40>;
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interrupts = <50 0>, <51 0>, <52 0>, <53 0>;
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status = "disabled";
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clocks = <&gclk 8>, <&mclk 0x14 13>;
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clock-names = "GCLK", "MCLK";
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};
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sercom2: sercom@41012000 {
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compatible = "atmel,sam0-sercom";
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reg = <0x41012000 0x40>;
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interrupts = <54 0>, <55 0>, <56 0>, <57 0>;
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status = "disabled";
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clocks = <&gclk 23>, <&mclk 0x18 9>;
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clock-names = "GCLK", "MCLK";
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};
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sercom3: sercom@41014000 {
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compatible = "atmel,sam0-sercom";
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reg = <0x41014000 0x40>;
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interrupts = <58 0>, <59 0>, <60 0>, <61 0>;
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status = "disabled";
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clocks = <&gclk 24>, <&mclk 0x18 10>;
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clock-names = "GCLK", "MCLK";
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};
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sercom4: sercom@43000000 {
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compatible = "atmel,sam0-sercom";
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reg = <0x43000000 0x40>;
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interrupts = <62 0>, <63 0>, <64 0>, <65 0>;
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status = "disabled";
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clocks = <&gclk 34>, <&mclk 0x20 0>;
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clock-names = "GCLK", "MCLK";
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};
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sercom5: sercom@43000400 {
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compatible = "atmel,sam0-sercom";
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reg = <0x43000400 0x40>;
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interrupts = <66 0>, <67 0>, <68 0>, <69 0>;
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status = "disabled";
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clocks = <&gclk 35>, <&mclk 0x20 1>;
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clock-names = "GCLK", "MCLK";
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};
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sercom6: sercom@43000800 {
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compatible = "atmel,sam0-sercom";
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reg = <0x43000800 0x40>;
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interrupts = <70 0>, <71 0>, <72 0>, <73 0>;
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status = "disabled";
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clocks = <&gclk 36>, <&mclk 0x20 2>;
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clock-names = "GCLK", "MCLK";
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};
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sercom7: sercom@43000c00 {
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compatible = "atmel,sam0-sercom";
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reg = <0x43000C00 0x40>;
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interrupts = <74 0>, <75 0>, <76 0>, <77 0>;
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status = "disabled";
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clocks = <&gclk 37>, <&mclk 0x20 3>;
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clock-names = "GCLK", "MCLK";
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};
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pinctrl: pinctrl@41008000 {
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compatible = "atmel,sam0-pinctrl";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x41008000 0x41008000 0x200>;
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porta: gpio@41008000 {
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compatible = "atmel,sam0-gpio";
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reg = <0x41008000 0x80>;
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gpio-controller;
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#gpio-cells = <2>;
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#atmel,pin-cells = <2>;
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};
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portb: gpio@41008080 {
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compatible = "atmel,sam0-gpio";
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reg = <0x41008080 0x80>;
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gpio-controller;
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#gpio-cells = <2>;
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#atmel,pin-cells = <2>;
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};
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portc: gpio@41008100 {
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compatible = "atmel,sam0-gpio";
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reg = <0x41008100 0x80>;
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gpio-controller;
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#gpio-cells = <2>;
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#atmel,pin-cells = <2>;
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};
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portd: gpio@41008180 {
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compatible = "atmel,sam0-gpio";
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reg = <0x41008180 0x80>;
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gpio-controller;
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#gpio-cells = <2>;
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#atmel,pin-cells = <2>;
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};
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};
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usb0: usb@41000000 {
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compatible = "atmel,sam0-usb";
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status = "disabled";
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reg = <0x41000000 0x1000>;
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interrupts = <80 0>, <81 0>, <82 0>, <83 0>;
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num-bidir-endpoints = <8>;
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};
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trng: random@42002800 {
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compatible = "atmel,sam-trng";
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reg = <0x42002800 0x1e>;
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peripheral-id = <0>;
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interrupts = <131 0>;
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};
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rtc: rtc@40002400 {
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compatible = "atmel,sam0-rtc";
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reg = <0x40002400 0x1C>;
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interrupts = <11 0>;
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clock-generator = <0>;
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status = "disabled";
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};
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adc0: adc@43001c00 {
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compatible = "atmel,sam0-adc";
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reg = <0x43001C00 0x4A>;
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interrupts = <118 0>, <119 0>;
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interrupt-names = "overrun", "resrdy";
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/*
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* 16 MHz max, source clock must not exceed 100 MHz.
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* - table 54-8, section 54.6, page 2020
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* - table 54-24, section 54.10.4, page 2031
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* -> 48 MHz GCLK(2) / 4 = 12 MHz
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*/
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gclk = <2>;
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prescaler = <4>;
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#io-channel-cells = <1>;
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clocks = <&gclk 40>, <&mclk 0x20 7>;
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clock-names = "GCLK", "MCLK";
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calib-offset = <0>;
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};
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adc1: adc@43002000 {
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compatible = "atmel,sam0-adc";
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reg = <0x43002000 0x4A>;
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interrupts = <120 0>, <121 0>;
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interrupt-names = "overrun", "resrdy";
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/*
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* 16 MHz max, source clock must not exceed 100 MHz.
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* - table 54-8, section 54.6, page 2020
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* - table 54-24, section 54.10.4, page 2031
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* -> 48 MHz GCLK(2) / 4 = 12 MHz
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*/
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gclk = <2>;
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prescaler = <4>;
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#io-channel-cells = <1>;
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clocks = <&gclk 41>, <&mclk 0x20 8>;
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clock-names = "GCLK", "MCLK";
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calib-offset = <14>;
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};
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tc0: tc@40003800 {
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compatible = "atmel,sam0-tc32";
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reg = <0x40003800 0x34>;
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interrupts = <107 0>;
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clocks = <&gclk 9>, <&mclk 0x14 14>;
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clock-names = "GCLK", "MCLK";
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};
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tc2: tc@4101a000 {
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compatible = "atmel,sam0-tc32";
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reg = <0x4101A000 0x34>;
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interrupts = <109 0>;
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clocks = <&gclk 26>, <&mclk 0x18 13>;
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clock-names = "GCLK", "MCLK";
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};
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tc4: tc@42001400 {
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compatible = "atmel,sam0-tc32";
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reg = <0x42001400 0x34>;
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interrupts = <111 0>;
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clocks = <&gclk 30>, <&mclk 0x1c 5>;
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clock-names = "GCLK", "MCLK";
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};
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tc6: tc@43001400 {
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compatible = "atmel,sam0-tc32";
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reg = <0x43001400 0x34>;
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interrupts = <113 0>;
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clocks = <&gclk 39>, <&mclk 0x20 5>;
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clock-names = "GCLK", "MCLK";
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};
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tcc0: tcc@41016000 {
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compatible = "atmel,sam0-tcc";
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reg = <0x41016000 0x2000>;
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interrupts = <85 0>, <86 0>, <87 0>, <88 0>, <89 0>,
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<90 0>, <91 0>;
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clocks = <&gclk 25>, <&mclk 0x18 11>;
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clock-names = "GCLK", "MCLK";
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channels = <6>;
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counter-size = <24>;
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};
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tcc1: tcc@41018000 {
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compatible = "atmel,sam0-tcc";
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reg = <0x41018000 0x2000>;
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interrupts = <92 0>, <93 0>, <94 0>, <95 0>, <96 0>;
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clocks = <&gclk 25>, <&mclk 0x18 12>;
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clock-names = "GCLK", "MCLK";
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channels = <4>;
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counter-size = <24>;
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};
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tcc2: tcc@42000c00 {
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compatible = "atmel,sam0-tcc";
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reg = <0x42000c00 0x400>;
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interrupts = <97 0>, <98 0>, <99 0>, <100 0>;
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clocks = <&gclk 29>, <&mclk 0x1c 3>;
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clock-names = "GCLK", "MCLK";
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channels = <3>;
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counter-size = <16>;
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};
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tcc3: tcc@42001000 {
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compatible = "atmel,sam0-tcc";
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reg = <0x42001000 0x400>;
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interrupts = <101 0>, <102 0>, <103 0>;
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clocks = <&gclk 29>, <&mclk 0x1c 4>;
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clock-names = "GCLK", "MCLK";
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channels = <2>;
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counter-size = <16>;
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};
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tcc4: tcc@43001000 {
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compatible = "atmel,sam0-tcc";
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reg = <0x43001000 0x400>;
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interrupts = <104 0>, <105 0>, <106 0>;
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clocks = <&gclk 38>, <&mclk 0x20 4>;
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clock-names = "GCLK", "MCLK";
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channels = <2>;
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counter-size = <16>;
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <3>;
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};
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