268 lines
7.5 KiB
C
268 lines
7.5 KiB
C
/*
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* Copyright 2022 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/drivers/counter.h>
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#include <zephyr/logging/log.h>
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#include <zephyr/irq.h>
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#include <soc.h>
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#include <Stm_Ip.h>
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LOG_MODULE_REGISTER(nxp_s32_sys_timer, CONFIG_COUNTER_LOG_LEVEL);
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#define SYS_TIMER_NODE(n) DT_NODELABEL(stm##n)
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#define SYS_TIMER_MAX_VALUE 0xFFFFFFFFU
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#define SYS_TIMER_NUM_CHANNELS 4
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#define SYS_TIMER_INSTANCE_ID(n) (n + 3 + CONFIG_NXP_S32_RTU_INDEX * 4)
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#define _SYS_TIMER_ISR(r, n) RTU##r##_STM_##n##_ISR
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#define SYS_TIMER_ISR(r, n) _SYS_TIMER_ISR(r, n)
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struct nxp_s32_sys_timer_chan_data {
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counter_alarm_callback_t callback;
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void *user_data;
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};
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struct nxp_s32_sys_timer_data {
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struct nxp_s32_sys_timer_chan_data ch_data[SYS_TIMER_NUM_CHANNELS];
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};
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struct nxp_s32_sys_timer_config {
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struct counter_config_info info;
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Stm_Ip_InstanceConfigType hw_cfg;
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Stm_Ip_ChannelConfigType ch_cfg[SYS_TIMER_NUM_CHANNELS];
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uint8_t instance;
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};
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static int nxp_s32_sys_timer_start(const struct device *dev)
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{
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const struct nxp_s32_sys_timer_config *config = dev->config;
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Stm_Ip_StartTimer(config->instance, 0);
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return 0;
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}
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static int nxp_s32_sys_timer_stop(const struct device *dev)
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{
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const struct nxp_s32_sys_timer_config *config = dev->config;
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Stm_Ip_StopTimer(config->instance);
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return 0;
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}
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static int nxp_s32_sys_timer_get_value(const struct device *dev, uint32_t *ticks)
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{
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const struct nxp_s32_sys_timer_config *config = dev->config;
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*ticks = Stm_Ip_GetCounterValue(config->instance);
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return 0;
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}
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static int nxp_s32_sys_timer_set_alarm(const struct device *dev, uint8_t chan_id,
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const struct counter_alarm_cfg *alarm_cfg)
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{
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const struct nxp_s32_sys_timer_config *config = dev->config;
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struct nxp_s32_sys_timer_data *data = dev->data;
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struct nxp_s32_sys_timer_chan_data *ch_data = &data->ch_data[chan_id];
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uint32_t ticks = alarm_cfg->ticks;
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if (ch_data->callback) {
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return -EBUSY;
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}
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if (ticks > config->info.max_top_value) {
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LOG_ERR("Invalid ticks value %d", ticks);
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return -EINVAL;
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}
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ch_data->callback = alarm_cfg->callback;
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ch_data->user_data = alarm_cfg->user_data;
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/* Disable the channel before loading the new value so that it takes effect immediately */
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Stm_Ip_DisableChannel(config->instance, chan_id);
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if (alarm_cfg->flags & COUNTER_ALARM_CFG_ABSOLUTE) {
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Stm_Ip_StartCountingAbsolute(config->instance, chan_id, ticks);
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} else {
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Stm_Ip_StartCounting(config->instance, chan_id, ticks);
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}
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return 0;
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}
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static int nxp_s32_sys_timer_cancel_alarm(const struct device *dev, uint8_t chan_id)
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{
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const struct nxp_s32_sys_timer_config *config = dev->config;
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struct nxp_s32_sys_timer_data *data = dev->data;
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struct nxp_s32_sys_timer_chan_data *ch_data = &data->ch_data[chan_id];
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Stm_Ip_DisableChannel(config->instance, chan_id);
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ch_data->callback = NULL;
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ch_data->user_data = NULL;
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return 0;
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}
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static uint32_t nxp_s32_sys_timer_get_pending_int(const struct device *dev)
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{
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const struct nxp_s32_sys_timer_config *config = dev->config;
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uint32_t flags = 0;
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uint8_t i;
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for (i = 0; i < counter_get_num_of_channels(dev); i++) {
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flags = Stm_Ip_GetInterruptFlag(config->instance, i);
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if (flags) {
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break;
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}
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}
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return flags;
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}
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static int nxp_s32_sys_timer_set_top_value(const struct device *dev,
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const struct counter_top_cfg *cfg)
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{
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ARG_UNUSED(dev);
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ARG_UNUSED(cfg);
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/* Overflow is fixed and cannot be changed */
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return -ENOTSUP;
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}
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static uint32_t nxp_s32_sys_timer_get_top_value(const struct device *dev)
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{
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const struct nxp_s32_sys_timer_config *config = dev->config;
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return config->info.max_top_value;
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}
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static uint32_t nxp_s32_sys_timer_get_frequency(const struct device *dev)
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{
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const struct nxp_s32_sys_timer_config *config = dev->config;
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return config->info.freq / (config->hw_cfg.clockPrescaler + 1U);
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}
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static int nxp_s32_sys_timer_init(const struct device *dev)
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{
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const struct nxp_s32_sys_timer_config *config = dev->config;
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struct nxp_s32_sys_timer_data *data = dev->data;
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struct nxp_s32_sys_timer_chan_data *ch_data;
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int i;
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Stm_Ip_Init(config->instance, &config->hw_cfg);
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for (i = 0; i < counter_get_num_of_channels(dev); i++) {
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ch_data = &data->ch_data[i];
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ch_data->callback = NULL;
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ch_data->user_data = NULL;
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Stm_Ip_InitChannel(config->instance, &config->ch_cfg[i]);
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}
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return 0;
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}
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static const struct counter_driver_api nxp_s32_sys_timer_driver_api = {
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.start = nxp_s32_sys_timer_start,
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.stop = nxp_s32_sys_timer_stop,
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.get_value = nxp_s32_sys_timer_get_value,
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.set_alarm = nxp_s32_sys_timer_set_alarm,
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.cancel_alarm = nxp_s32_sys_timer_cancel_alarm,
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.set_top_value = nxp_s32_sys_timer_set_top_value,
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.get_pending_int = nxp_s32_sys_timer_get_pending_int,
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.get_top_value = nxp_s32_sys_timer_get_top_value,
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.get_freq = nxp_s32_sys_timer_get_frequency
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};
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#define SYS_TIMER_CHANNEL_CFG(i, n) \
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{ \
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.hwChannel = i, \
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.callback = &nxp_s32_sys_timer_##n##_callback, \
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.callbackParam = i, \
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.channelMode = STM_IP_CH_MODE_ONESHOT, \
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}
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#define SYS_TIMER_ISR_DECLARE(n) \
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extern void SYS_TIMER_ISR(CONFIG_NXP_S32_RTU_INDEX, n)(void)
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#define SYS_TIMER_INIT_DEVICE(n) \
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SYS_TIMER_ISR_DECLARE(n); \
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\
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void nxp_s32_sys_timer_##n##_callback(uint8_t chan_id) \
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{ \
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const struct device *dev = DEVICE_DT_GET(SYS_TIMER_NODE(n)); \
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const struct nxp_s32_sys_timer_config *config = dev->config; \
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struct nxp_s32_sys_timer_data *data = dev->data; \
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struct nxp_s32_sys_timer_chan_data *ch_data = &data->ch_data[chan_id]; \
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counter_alarm_callback_t cb = ch_data->callback; \
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uint32_t val; \
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\
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ch_data->callback = NULL; \
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if (cb) { \
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val = Stm_Ip_GetCounterValue(config->instance); \
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cb(dev, chan_id, val, ch_data->user_data); \
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} \
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} \
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\
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static int nxp_s32_sys_timer_##n##_init(const struct device *dev) \
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{ \
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IRQ_CONNECT(DT_IRQN(SYS_TIMER_NODE(n)), \
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DT_IRQ(SYS_TIMER_NODE(n), priority), \
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SYS_TIMER_ISR(CONFIG_NXP_S32_RTU_INDEX, n), \
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DEVICE_DT_GET(SYS_TIMER_NODE(n)), \
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DT_IRQ(SYS_TIMER_NODE(n), flags)); \
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irq_enable(DT_IRQN(SYS_TIMER_NODE(n))); \
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\
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return nxp_s32_sys_timer_init(dev); \
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} \
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\
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static struct nxp_s32_sys_timer_data nxp_s32_sys_timer_data_##n; \
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\
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static const struct nxp_s32_sys_timer_config nxp_s32_sys_timer_config_##n = { \
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.info = { \
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.max_top_value = SYS_TIMER_MAX_VALUE, \
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.freq = (DT_PROP(SYS_TIMER_NODE(n), clock_frequency)), \
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.channels = SYS_TIMER_NUM_CHANNELS, \
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.flags = COUNTER_CONFIG_INFO_COUNT_UP, \
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}, \
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.hw_cfg = { \
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.stopInDebugMode = DT_PROP(SYS_TIMER_NODE(n), freeze), \
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.clockPrescaler = DT_PROP(SYS_TIMER_NODE(n), prescaler) - 1, \
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}, \
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.ch_cfg = { \
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LISTIFY(SYS_TIMER_NUM_CHANNELS, SYS_TIMER_CHANNEL_CFG, (,), n) \
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}, \
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.instance = SYS_TIMER_INSTANCE_ID(n), \
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}; \
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\
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DEVICE_DT_DEFINE(SYS_TIMER_NODE(n), \
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nxp_s32_sys_timer_##n##_init, \
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NULL, \
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&nxp_s32_sys_timer_data_##n, \
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&nxp_s32_sys_timer_config_##n, \
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POST_KERNEL, \
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CONFIG_COUNTER_INIT_PRIORITY, \
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&nxp_s32_sys_timer_driver_api);
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#if DT_NODE_HAS_STATUS(SYS_TIMER_NODE(0), okay)
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SYS_TIMER_INIT_DEVICE(0)
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#endif
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#if DT_NODE_HAS_STATUS(SYS_TIMER_NODE(1), okay)
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SYS_TIMER_INIT_DEVICE(1)
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#endif
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#if DT_NODE_HAS_STATUS(SYS_TIMER_NODE(2), okay)
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SYS_TIMER_INIT_DEVICE(2)
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#endif
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#if DT_NODE_HAS_STATUS(SYS_TIMER_NODE(3), okay)
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SYS_TIMER_INIT_DEVICE(3)
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#endif
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