158 lines
5.8 KiB
C
158 lines
5.8 KiB
C
/*
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* Copyright (c) 2022 Henrik Brix Andersen <henrik@brixandersen.dk>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_DRIVERS_CAN_SJA1000_H_
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#define ZEPHYR_DRIVERS_CAN_SJA1000_H_
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#include <zephyr/drivers/can.h>
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/* Output Control Register (OCR) bits */
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#define CAN_SJA1000_OCR_OCMODE_MASK GENMASK(1, 0)
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#define CAN_SJA1000_OCR_OCPOL0 BIT(2)
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#define CAN_SJA1000_OCR_OCTN0 BIT(3)
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#define CAN_SJA1000_OCR_OCTP0 BIT(4)
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#define CAN_SJA1000_OCR_OCPOL1 BIT(5)
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#define CAN_SJA1000_OCR_OCTN1 BIT(6)
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#define CAN_SJA1000_OCR_OCTP1 BIT(7)
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#define CAN_SJA1000_OCR_OCMODE_BIPHASE FIELD_PREP(CAN_SJA1000_OCR_OCMODE_MASK, 0U)
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#define CAN_SJA1000_OCR_OCMODE_TEST FIELD_PREP(CAN_SJA1000_OCR_OCMODE_MASK, 1U)
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#define CAN_SJA1000_OCR_OCMODE_NORMAL FIELD_PREP(CAN_SJA1000_OCR_OCMODE_MASK, 2U)
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#define CAN_SJA1000_OCR_OCMODE_CLOCK FIELD_PREP(CAN_SJA1000_OCR_OCMODE_MASK, 3U)
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/* Clock Divider Register (CDR) bits */
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#define CAN_SJA1000_CDR_CD_MASK GENMASK(2, 0)
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#define CAN_SJA1000_CDR_CLOCK_OFF BIT(3)
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#define CAN_SJA1000_CDR_RXINTEN BIT(5)
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#define CAN_SJA1000_CDR_CBP BIT(6)
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#define CAN_SJA1000_CDR_CAN_MODE BIT(7)
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#define CAN_SJA1000_CDR_CD_DIV1 FIELD_PREP(CAN_SJA1000_CDR_CD_MASK, 7U)
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#define CAN_SJA1000_CDR_CD_DIV2 FIELD_PREP(CAN_SJA1000_CDR_CD_MASK, 0U)
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#define CAN_SJA1000_CDR_CD_DIV4 FIELD_PREP(CAN_SJA1000_CDR_CD_MASK, 1U)
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#define CAN_SJA1000_CDR_CD_DIV6 FIELD_PREP(CAN_SJA1000_CDR_CD_MASK, 2U)
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#define CAN_SJA1000_CDR_CD_DIV8 FIELD_PREP(CAN_SJA1000_CDR_CD_MASK, 3U)
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#define CAN_SJA1000_CDR_CD_DIV10 FIELD_PREP(CAN_SJA1000_CDR_CD_MASK, 4U)
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#define CAN_SJA1000_CDR_CD_DIV12 FIELD_PREP(CAN_SJA1000_CDR_CD_MASK, 5U)
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#define CAN_SJA1000_CDR_CD_DIV14 FIELD_PREP(CAN_SJA1000_CDR_CD_MASK, 6U)
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#define CAN_SJA1000_TIMING_MIN_INITIALIZER \
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{ \
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.sjw = 1, \
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.prop_seg = 0, \
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.phase_seg1 = 1, \
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.phase_seg2 = 1, \
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.prescaler = 1 \
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}
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#define CAN_SJA1000_TIMING_MAX_INITIALIZER \
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{ \
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.sjw = 4, \
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.prop_seg = 0, \
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.phase_seg1 = 16, \
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.phase_seg2 = 8, \
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.prescaler = 64 \
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}
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typedef void (*can_sja1000_write_reg_t)(const struct device *dev, uint8_t reg, uint8_t val);
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typedef uint8_t (*can_sja1000_read_reg_t)(const struct device *dev, uint8_t reg);
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struct can_sja1000_config {
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can_sja1000_read_reg_t read_reg;
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can_sja1000_write_reg_t write_reg;
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uint32_t bitrate;
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uint32_t sample_point;
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uint32_t sjw;
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uint32_t phase_seg1;
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uint32_t phase_seg2;
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const struct device *phy;
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uint32_t max_bitrate;
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uint8_t ocr;
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uint8_t cdr;
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const void *custom;
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};
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#define CAN_SJA1000_DT_CONFIG_GET(node_id, _custom, _read_reg, _write_reg, _ocr, _cdr) \
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{ \
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.read_reg = _read_reg, .write_reg = _write_reg, \
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.bitrate = DT_PROP(node_id, bus_speed), .sjw = DT_PROP(node_id, sjw), \
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.phase_seg1 = DT_PROP_OR(node_id, phase_seg1, 0), \
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.phase_seg2 = DT_PROP_OR(node_id, phase_seg2, 0), \
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.sample_point = DT_PROP_OR(node_id, sample_point, 0), \
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.max_bitrate = DT_CAN_TRANSCEIVER_MAX_BITRATE(node_id, 1000000), \
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.phy = DEVICE_DT_GET_OR_NULL(DT_PHANDLE(node_id, phys)), \
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.ocr = _ocr, .cdr = _cdr, .custom = _custom, \
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}
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#define CAN_SJA1000_DT_CONFIG_INST_GET(inst, _custom, _read_reg, _write_reg, _ocr, _cdr) \
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CAN_SJA1000_DT_CONFIG_GET(DT_DRV_INST(inst), _custom, _read_reg, _write_reg, _ocr, _cdr)
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struct can_sja1000_rx_filter {
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struct can_filter filter;
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can_rx_callback_t callback;
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void *user_data;
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};
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struct can_sja1000_data {
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ATOMIC_DEFINE(rx_allocs, CONFIG_CAN_MAX_FILTER);
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struct can_sja1000_rx_filter filters[CONFIG_CAN_MAX_FILTER];
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struct k_mutex mod_lock;
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bool started;
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can_mode_t mode;
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enum can_state state;
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can_state_change_callback_t state_change_cb;
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void *state_change_cb_data;
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struct k_sem tx_idle;
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can_tx_callback_t tx_callback;
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void *tx_user_data;
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uint32_t sjw;
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void *custom;
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};
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#define CAN_SJA1000_DATA_INITIALIZER(_custom) \
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{ \
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.custom = _custom, \
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}
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int can_sja1000_set_timing(const struct device *dev, const struct can_timing *timing);
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int can_sja1000_get_capabilities(const struct device *dev, can_mode_t *cap);
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int can_sja1000_start(const struct device *dev);
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int can_sja1000_stop(const struct device *dev);
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int can_sja1000_set_mode(const struct device *dev, can_mode_t mode);
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int can_sja1000_send(const struct device *dev, const struct can_frame *frame, k_timeout_t timeout,
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can_tx_callback_t callback, void *user_data);
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int can_sja1000_add_rx_filter(const struct device *dev, can_rx_callback_t callback, void *user_data,
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const struct can_filter *filter);
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void can_sja1000_remove_rx_filter(const struct device *dev, int filter_id);
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#ifndef CONFIG_CAN_AUTO_BUS_OFF_RECOVERY
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int can_sja1000_recover(const struct device *dev, k_timeout_t timeout);
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#endif /* !CONFIG_CAN_AUTO_BUS_OFF_RECOVERY */
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int can_sja1000_get_state(const struct device *dev, enum can_state *state,
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struct can_bus_err_cnt *err_cnt);
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void can_sja1000_set_state_change_callback(const struct device *dev,
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can_state_change_callback_t callback, void *user_data);
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int can_sja1000_get_max_filters(const struct device *dev, bool ide);
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int can_sja1000_get_max_bitrate(const struct device *dev, uint32_t *max_bitrate);
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void can_sja1000_isr(const struct device *dev);
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int can_sja1000_init(const struct device *dev);
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#endif /* ZEPHYR_DRIVERS_CAN_SJA1000_H_ */
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