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https://github.com/zephyrproject-rtos/zephyr.git
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fc79380dc7
Introduce this board, rcc config: the SoC uses slightly different domain naming, eg: `cdppre` is equivalent to `d1ppre` D1 = CD D2 = CD<..>2 D3 = SRD Signed-off-by: Manojkumar Subramaniam <manoj@electrolance.com>
37 lines
1.0 KiB
Plaintext
37 lines
1.0 KiB
Plaintext
/*
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* Copyright (c) 2021 Electrolance Solutions
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/ {
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arduino_header: connector {
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compatible = "arduino-header-r3";
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#gpio-cells = <2>;
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gpio-map-mask = <0xffffffff 0xffffffc0>;
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gpio-map-pass-thru = <0 0x3f>;
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gpio-map = <0 0 &gpioa 3 0>, /* A0 */
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<1 0 &gpioc 0 0>, /* A1 */
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<2 0 &gpioc 3 0>, /* A2 */
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<3 0 &gpiob 1 0>, /* A3 */
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<4 0 &gpioc 2 0>, /* A4 */
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<5 0 &gpiof 11 0>, /* A5 */
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<6 0 &gpiob 7 0>, /* D0 */
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<7 0 &gpiob 6 0>, /* D1 */
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<8 0 &gpiog 14 0>, /* D2 */
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<9 0 &gpioe 13 0>, /* D3 */
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<10 0 &gpioe 14 0>, /* D4 */
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<11 0 &gpioe 11 0>, /* D5 */
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<12 0 &gpioa 8 0>, /* D6 */
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<13 0 &gpiog 12 0>, /* D7 */
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<14 0 &gpiog 9 0>, /* D8 */
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<15 0 &gpiod 15 0>, /* D9 */
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<16 0 &gpiod 14 0>, /* D10 */
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<17 0 &gpioa 7 0>, /* D11 */
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<18 0 &gpioa 6 0>, /* D12 */
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<19 0 &gpioa 5 0>, /* D13 */
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<20 0 &gpiob 9 0>, /* D14 */
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<21 0 &gpiob 8 0>; /* D15 */
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};
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};
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