64 lines
1.0 KiB
Plaintext
64 lines
1.0 KiB
Plaintext
/*
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* Copyright (c) 2019, NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <nxp/nxp_lpc55S6x_ns.dtsi>
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#include "lpcxpresso55s69.dtsi"
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/ {
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model = "NXP LPCXpresso55S69 board";
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compatible = "nxp,lpc55xxx", "nxp,lpc";
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cpus {
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/delete-node/ cpu@0;
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};
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chosen {
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zephyr,sram = &sram3;
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zephyr,flash = &flash0;
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zephyr,code-partition = &slot1_partition;
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zephyr,entropy = &rng;
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};
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};
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/*
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* Default for this board is to allocate SRAM3-4 to cpu1 but the
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* application can have an application specific device tree to
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* allocate the SRAM0-4 differently.
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*
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* For example, SRAM0-3 could be allocated to cpu0 with only SRAM4
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* for cpu1. This would require the zephyr,sram chosen value for cpu1
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* to be changed to sram4 and the value of sram0 to have a DT_SIZE_K
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* of 256.
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*
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*/
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&sram3 {
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compatible = "mmio-sram";
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reg = <0x20030000 DT_SIZE_K(80)>;
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};
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&gpio0 {
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status = "okay";
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};
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&gpio1 {
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status = "okay";
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};
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&blue_led {
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status = "okay";
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};
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&mailbox0 {
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status = "okay";
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};
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&mma8652fc {
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status = "disabled";
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};
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