351 lines
8.7 KiB
C
351 lines
8.7 KiB
C
/*
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* Copyright (c) 2016 Open-RnD Sp. z o.o.
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* Copyright (c) 2016 Linaro Limited.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @brief Driver for Reset & Clock Control of STM32F4X family processor.
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*
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* Based on reference manual:
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* RM0368 Reference manual STM32F401xB/C and STM32F401xD/E
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* advanced ARM ® -based 32-bit MCUs
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*
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* Chapter 6. Reset and Clock control (RCC) for STM43F401xB/C and STM32F401xD/E
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*/
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#include <soc.h>
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#include <soc_registers.h>
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#include <clock_control.h>
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#include <misc/util.h>
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#include <clock_control/stm32_clock_control.h>
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struct stm32f4x_rcc_data {
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uint8_t *base;
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};
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static inline int stm32f4x_clock_control_on(struct device *dev,
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clock_control_subsys_t sub_system)
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{
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struct stm32f4x_rcc_data *data = dev->driver_data;
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volatile struct stm32f4x_rcc *rcc = (struct stm32f4x_rcc *)(data->base);
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struct stm32f4x_pclken *pclken = (struct stm32f4x_pclken *)(sub_system);
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uint32_t tmpreg = 0; /* Register delay helper */
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switch (pclken->bus) {
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case STM32F4X_CLOCK_BUS_AHB1:
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rcc->ahb1enr |= pclken->enr;
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tmpreg = rcc->ahb1enr;
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break;
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case STM32F4X_CLOCK_BUS_AHB2:
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rcc->ahb2enr |= pclken->enr;
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tmpreg = rcc->ahb2enr;
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break;
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case STM32F4X_CLOCK_BUS_APB1:
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rcc->apb1enr |= pclken->enr;
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tmpreg = rcc->apb1enr;
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break;
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case STM32F4X_CLOCK_BUS_APB2:
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rcc->apb2enr |= pclken->enr;
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tmpreg = rcc->apb2enr;
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break;
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}
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return 0;
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}
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static inline int stm32f4x_clock_control_off(struct device *dev,
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clock_control_subsys_t sub_system)
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{
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struct stm32f4x_rcc_data *data = dev->driver_data;
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volatile struct stm32f4x_rcc *rcc = (struct stm32f4x_rcc *)(data->base);
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struct stm32f4x_pclken *pclken = (struct stm32f4x_pclken *)(sub_system);
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uint32_t tmpreg = 0; /* Register delay helper */
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switch (pclken->bus) {
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case STM32F4X_CLOCK_BUS_AHB1:
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rcc->ahb1enr &= ~pclken->enr;
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tmpreg = rcc->ahb1enr;
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break;
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case STM32F4X_CLOCK_BUS_AHB2:
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rcc->ahb2enr &= ~pclken->enr;
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tmpreg = rcc->ahb2enr;
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break;
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case STM32F4X_CLOCK_BUS_APB1:
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rcc->apb1enr &= ~pclken->enr;
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tmpreg = rcc->apb1enr;
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break;
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case STM32F4X_CLOCK_BUS_APB2:
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rcc->apb2enr &= ~pclken->enr;
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tmpreg = rcc->apb2enr;
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break;
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}
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return 0;
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}
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/**
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* @brief helper for mapping a setting to register value
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*/
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struct regval_map {
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int val;
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int reg;
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};
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static int map_reg_val(const struct regval_map *map, size_t cnt, int val)
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{
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for (int i = 0; i < cnt; i++) {
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if (map[i].val == val) {
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return map[i].reg;
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}
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}
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return 0;
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}
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/**
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* @brief map APB prescaler setting to register value
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*/
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static int __apb_prescaler(int prescaler)
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{
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if (prescaler == 0) {
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return STM32F4X_RCC_CFG_HCLK_DIV_0;
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}
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const struct regval_map map[] = {
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{0, STM32F4X_RCC_CFG_HCLK_DIV_0},
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{2, STM32F4X_RCC_CFG_HCLK_DIV_2},
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{4, STM32F4X_RCC_CFG_HCLK_DIV_4},
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{8, STM32F4X_RCC_CFG_HCLK_DIV_8},
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{16, STM32F4X_RCC_CFG_HCLK_DIV_16},
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};
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return map_reg_val(map, ARRAY_SIZE(map), prescaler);
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}
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/**
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* @brief map AHB prescaler setting to register value
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*/
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static int __ahb_prescaler(int prescaler)
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{
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if (prescaler == 0) {
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return STM32F4X_RCC_CFG_SYSCLK_DIV_0;
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}
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const struct regval_map map[] = {
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{0, STM32F4X_RCC_CFG_SYSCLK_DIV_0},
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{2, STM32F4X_RCC_CFG_SYSCLK_DIV_2},
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{4, STM32F4X_RCC_CFG_SYSCLK_DIV_4},
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{8, STM32F4X_RCC_CFG_SYSCLK_DIV_8},
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{16, STM32F4X_RCC_CFG_SYSCLK_DIV_16},
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{64, STM32F4X_RCC_CFG_SYSCLK_DIV_64},
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{128, STM32F4X_RCC_CFG_SYSCLK_DIV_128},
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{256, STM32F4X_RCC_CFG_SYSCLK_DIV_256},
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{512, STM32F4X_RCC_CFG_SYSCLK_DIV_512},
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};
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return map_reg_val(map, ARRAY_SIZE(map), prescaler);
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}
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#ifdef CONFIG_CLOCK_STM32F4X_SYSCLK_SRC_PLL
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/**
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* @brief map PPLP division factor to register value
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*/
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static int __pllp_div(int div)
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{
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if (div == 0) {
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return STM32F4X_RCC_CFG_PLLP_DIV_2;
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}
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const struct regval_map map[] = {
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{2, STM32F4X_RCC_CFG_PLLP_DIV_2},
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{4, STM32F4X_RCC_CFG_PLLP_DIV_4},
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{6, STM32F4X_RCC_CFG_PLLP_DIV_6},
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{8, STM32F4X_RCC_CFG_PLLP_DIV_8},
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};
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return map_reg_val(map, ARRAY_SIZE(map), div);
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}
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#endif /* CONFIG_CLOCK_STM32F4X_SYSCLK_SRC_PLL */
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static uint32_t __get_ahb_clock(uint32_t sysclk)
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{
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/* AHB clock is generated based on SYSCLK */
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uint32_t sysclk_div = CONFIG_CLOCK_STM32F4X_AHB_PRESCALER;
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if (sysclk_div == 0) {
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sysclk_div = 1;
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}
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return sysclk / sysclk_div;
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}
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static uint32_t __get_apb_clock(uint32_t ahb_clock, uint32_t prescaler)
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{
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if (prescaler == 0) {
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prescaler = 1;
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}
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return ahb_clock / prescaler;
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}
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static int stm32f4x_clock_control_get_subsys_rate(struct device *clock,
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clock_control_subsys_t sub_system,
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uint32_t *rate)
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{
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struct stm32f4x_pclken *pclken = (struct stm32f4x_pclken *)(sub_system);
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/* assumes SYSCLK is SYS_CLOCK_HW_CYCLES_PER_SEC */
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uint32_t ahb_clock =
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__get_ahb_clock(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC);
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uint32_t apb1_clock = __get_apb_clock(ahb_clock,
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CONFIG_CLOCK_STM32F4X_APB1_PRESCALER);
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uint32_t apb2_clock = __get_apb_clock(ahb_clock,
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CONFIG_CLOCK_STM32F4X_APB2_PRESCALER);
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ARG_UNUSED(clock);
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switch (pclken->bus) {
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case STM32F4X_CLOCK_BUS_AHB1:
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case STM32F4X_CLOCK_BUS_AHB2:
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*rate = ahb_clock;
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break;
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case STM32F4X_CLOCK_BUS_APB1:
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*rate = apb1_clock;
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break;
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case STM32F4X_CLOCK_BUS_APB2:
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*rate = apb2_clock;
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break;
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}
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return 0;
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}
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static struct clock_control_driver_api stm32f4x_clock_control_api = {
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.on = stm32f4x_clock_control_on,
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.off = stm32f4x_clock_control_off,
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.get_rate = stm32f4x_clock_control_get_subsys_rate,
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};
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static int stm32f4x_clock_control_init(struct device *dev)
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{
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struct stm32f4x_rcc_data *data = dev->driver_data;
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volatile struct stm32f4x_rcc *rcc =
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(struct stm32f4x_rcc *)(data->base);
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/* SYSCLK source defaults to HSI */
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int sysclk_src = STM32F4X_RCC_CFG_SYSCLK_SRC_HSI;
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uint32_t hpre = __ahb_prescaler(CONFIG_CLOCK_STM32F4X_AHB_PRESCALER);
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uint32_t ppre1 = __apb_prescaler(CONFIG_CLOCK_STM32F4X_APB1_PRESCALER);
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uint32_t ppre2 = __apb_prescaler(CONFIG_CLOCK_STM32F4X_APB2_PRESCALER);
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#ifdef CONFIG_CLOCK_STM32F4X_SYSCLK_SRC_PLL
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uint32_t pllmdiv = CONFIG_CLOCK_STM32F4X_PLLM_DIV_FACTOR;
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uint32_t pllnmul = CONFIG_CLOCK_STM32F4X_PLLN_MULTIPLIER;
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uint32_t pllpdiv = __pllp_div(CONFIG_CLOCK_STM32F4X_PLLP_DIV_FACTOR);
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uint32_t pllqdiv = CONFIG_CLOCK_STM32F4X_PLLQ_DIV_FACTOR;
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#endif /* CONFIG_CLOCK_STM32F4X_SYSCLK_SRC_PLL */
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/* Register delay helper */
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uint32_t tmpreg = 0;
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/* Enable power control clock */
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rcc->apb1enr |= STM32F4X_RCC_APB1ENR_PWREN;
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tmpreg = rcc->apb1enr;
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/* disable PLL */
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rcc->cr.bit.pllon = 0;
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/* disable HSE */
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rcc->cr.bit.hseon = 0;
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#ifdef CONFIG_CLOCK_STM32F4X_HSE_BYPASS
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/* HSE is disabled, HSE bypass can be enabled */
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rcc->cr.bit.hsebyp = 1;
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#endif
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#ifdef CONFIG_CLOCK_STM32F4X_PLL_SRC_HSI
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/* enable HSI clock */
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rcc->cr.bit.hsion = 1;
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/* this should end after one test */
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while (rcc->cr.bit.hsirdy != 1) {
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}
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/* TODO: should we care about HSI calibration adjustment? */
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/* PLL input from HSI */
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rcc->pllcfgr.bit.pllsrc = STM32F4X_RCC_CFG_PLL_SRC_HSI;
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#endif /* CONFIG_CLOCK_STM32F4X_PLL_SRC_HSI */
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#ifdef CONFIG_CLOCK_STM32F4X_PLL_SRC_HSE
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/* wait for to become ready */
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rcc->cr.bit.hseon = 1;
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while (rcc->cr.bit.hserdy != 1) {
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}
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/* TODO: should we disable HSI if HSE gets used? */
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rcc->pllcfgr.bit.pllsrc = STM32F4X_RCC_CFG_PLL_SRC_HSE;
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#endif /* CONFIG_CLOCK_STM32F4X_PLL_SRC_HSE */
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/* setup AHB prescaler */
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rcc->cfgr.bit.hpre = hpre;
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/* setup APB1, must not exceed 42MHz */
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rcc->cfgr.bit.ppre1 = ppre1;
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/* setup APB2 */
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rcc->cfgr.bit.ppre2 = ppre2;
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#ifdef CONFIG_CLOCK_STM32F4X_SYSCLK_SRC_PLL
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/* default set of dividers and multipliers (PLL must be disabled) */
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rcc->pllcfgr.bit.pllm = pllmdiv;
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rcc->pllcfgr.bit.plln = pllnmul;
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rcc->pllcfgr.bit.pllp = pllpdiv;
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rcc->pllcfgr.bit.pllq = pllqdiv;
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/* enable PLL */
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rcc->cr.bit.pllon = 1;
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/* wait for PLL to become ready */
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while (rcc->cr.bit.pllrdy != 1) {
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}
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sysclk_src = STM32F4X_RCC_CFG_SYSCLK_SRC_PLL;
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#elif defined(CONFIG_CLOCK_STM32F4X_SYSCLK_SRC_HSE)
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/* wait for to become ready */
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rcc->cr.bit.hseon = 1;
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while (rcc->cr.bit.hserdy != 1) {
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}
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sysclk_src = STM32F4X_RCC_CFG_SYSCLK_SRC_HSE;
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#endif
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/* configure flash access latency before SYSCLK source switch */
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__setup_flash();
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/* set SYSCLK clock value */
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rcc->cfgr.bit.sw = sysclk_src;
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/* wait for SYSCLK to switch the source */
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while (rcc->cfgr.bit.sws != sysclk_src) {
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}
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return 0;
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}
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static struct stm32f4x_rcc_data stm32f4x_rcc_data = {
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.base = (uint8_t *)RCC_BASE,
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};
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/* FIXME: move prescaler/multiplier defines into device config */
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/**
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* @brief RCC device, note that priority is intentionally set to 1 so
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* that the device init runs just after SOC init
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*/
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DEVICE_AND_API_INIT(rcc_stm32f4x, STM32_CLOCK_CONTROL_NAME,
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&stm32f4x_clock_control_init,
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&stm32f4x_rcc_data, NULL,
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PRE_KERNEL_1,
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CONFIG_CLOCK_CONTROL_STM32F4X_DEVICE_INIT_PRIORITY,
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&stm32f4x_clock_control_api);
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