141 lines
3.2 KiB
Plaintext
141 lines
3.2 KiB
Plaintext
# Kconfig - STM32L4 MCU clock control driver config
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#
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# Copyright (c) 2016 Open-RnD Sp. z o.o.
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# Copyright (c) 2016 BayLibre, SAS
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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if SOC_SERIES_STM32L4X
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menuconfig CLOCK_CONTROL_STM32L4X
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bool
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prompt "STM32L4x Reset & Clock Control"
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depends on CLOCK_CONTROL && SOC_SERIES_STM32L4X
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default y if SOC_SERIES_STM32L4X
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help
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Enable driver for Reset & Clock Control subsystem found
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in STM32L4 family of MCUs
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config CLOCK_CONTROL_STM32L4X_DEVICE_INIT_PRIORITY
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int "Clock Control Device Priority"
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default 1
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depends on CLOCK_CONTROL_STM32L4X
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help
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This option controls the priority of clock control
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device initialization. Higher priority ensures that the device
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is initialized earlier in the startup cycle. If unsure, leave
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at default value 1
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choice
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prompt "STM32L4X System Clock Source"
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depends on CLOCK_CONTROL_STM32L4X
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default CLOCK_STM32L4X_SYSCLK_SRC_PLL
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config CLOCK_STM32L4X_SYSCLK_SRC_HSE
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bool "HSE"
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help
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Use HSE as source of SYSCLK
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config CLOCK_STM32L4X_SYSCLK_SRC_PLL
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bool "PLL"
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help
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Use PLL as source of SYSCLK
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endchoice
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choice
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prompt "STM32L4X PLL Clock Source"
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depends on CLOCK_CONTROL_STM32L4X && CLOCK_STM32L4X_SYSCLK_SRC_PLL
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default CLOCK_STM32L4X_PLL_SRC_HSI
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config CLOCK_STM32L4X_PLL_SRC_MSI
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bool "MSI"
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help
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Use MSI as source of PLL
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config CLOCK_STM32L4X_PLL_SRC_HSI
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bool "HSI"
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help
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Use HSI as source of PLL
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endchoice
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config CLOCK_STM32L4X_HSE_BYPASS
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bool "HSE bypass"
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depends on CLOCK_CONTROL_STM32L4X && CLOCK_STM32L4X_SYSCLK_SRC_HSE
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help
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Enable this option to bypass external high-speed clock (HSE).
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config CLOCK_STM32L4X_PLL_DIVISOR
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int "PLL divisor"
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depends on CLOCK_CONTROL_STM32L4X && CLOCK_STM32L4X_SYSCLK_SRC_PLL
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default 1
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range 1 8
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help
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PLL divisor, allowed values: 1-8. With this ensure that the PLL
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VCO input frequency ranges from 4 to 16MHz.
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config CLOCK_STM32L4X_PLL_MULTIPLIER
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int "PLL multiplier"
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depends on CLOCK_CONTROL_STM32L4X && CLOCK_STM32L4X_SYSCLK_SRC_PLL
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default 20
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range 8 86
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help
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PLL multiplier, allowed values: 2-16. PLL output must not
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exceed 344MHz.
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config CLOCK_STM32L4X_PLL_P_DIVISOR
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int "PLL P Divisor"
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depends on CLOCK_CONTROL_STM32L4X
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default 7
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range 0 17
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help
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PLL P Output divisor, allowed values: 0, 7, 17.
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config CLOCK_STM32L4X_PLL_Q_DIVISOR
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int "PLL Q Divisor"
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depends on CLOCK_CONTROL_STM32L4X
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default 2
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range 0 8
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help
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PLL Q Output divisor, allowed values: 0, 2, 4, 6, 8.
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config CLOCK_STM32L4X_PLL_R_DIVISOR
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int "PLL R Divisor"
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depends on CLOCK_CONTROL_STM32L4X
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default 4
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range 0 8
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help
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PLL R Output divisor, allowed values: 0, 2, 4, 6, 8.
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config CLOCK_STM32L4X_AHB_PRESCALER
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int "AHB prescaler"
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depends on CLOCK_CONTROL_STM32L4X
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default 0
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range 0 512
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help
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AHB prescaler, allowed values: 0, 2, 4, 8, 16, 64, 128,
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256, 512.
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config CLOCK_STM32L4X_APB1_PRESCALER
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int "APB1 prescaler"
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depends on CLOCK_CONTROL_STM32L4X
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default 0
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range 0 16
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help
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APB1 Low speed clock (PCLK1) prescaler, allowed values:
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0, 2, 4, 8, 16
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config CLOCK_STM32L4X_APB2_PRESCALER
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int "APB2 prescaler"
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depends on CLOCK_CONTROL_STM32L4X
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default 0
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range 0 16
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help
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APB2 High speed clock (PCLK2) prescaler, allowed values:
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0, 2, 4, 8, 16
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endif
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