65 lines
1.4 KiB
Plaintext
65 lines
1.4 KiB
Plaintext
/*
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* Copyright (c) 2021 Telink Semiconductor
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @brief Linker script for the Telink B91 SoC
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*/
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#include <zephyr/devicetree.h>
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#include <zephyr/linker/linker-tool.h>
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MEMORY
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{
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ROM_INIT (rx) : ORIGIN = DT_REG_ADDR(DT_CHOSEN(zephyr_flash)), LENGTH = DT_REG_SIZE(DT_CHOSEN(zephyr_flash))
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RAM_ILM (rwx) : ORIGIN = DT_REG_ADDR(DT_NODELABEL(ram_ilm)), LENGTH = DT_REG_SIZE(DT_NODELABEL(ram_ilm))
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}
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SECTIONS
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{
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SECTION_PROLOGUE(vector,,)
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{
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. = ALIGN(4);
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KEEP(*(.init.*))
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} GROUP_LINK_IN(ROM_INIT)
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}
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#include <zephyr/arch/riscv/common/linker.ld>
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SECTIONS
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{
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SECTION_DATA_PROLOGUE(aes_data,,)
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{
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. = ALIGN(8);
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*(.aes_data)
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*(".aes_data.*")
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PROVIDE (_AES_DATA_VMA_END = .);
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PROVIDE (_AES_DATA_VMA_START = ADDR(aes_data));
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} GROUP_DATA_LINK_IN(RAM_ILM, ROMABLE_REGION)
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SECTION_DATA_PROLOGUE(retention_data,,)
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{
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. = ALIGN(8);
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*(.retention_data)
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*(".retention_data.*")
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PROVIDE (_RETENTION_DATA_VMA_END = .);
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PROVIDE (_RETENTION_DATA_VMA_START = ADDR(retention_data));
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PROVIDE (_RETENTION_DATA_LMA_START = LOADADDR(retention_data));
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} GROUP_DATA_LINK_IN(RAM_ILM, ROMABLE_REGION)
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SECTION_DATA_PROLOGUE(ram_code,,)
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{
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. = ALIGN(8);
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*(.ram_code)
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*(".ram_code.*")
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PROVIDE (_RAMCODE_VMA_END = .);
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PROVIDE (_RAMCODE_VMA_START = ADDR(ram_code));
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PROVIDE (_RAMCODE_LMA_START = LOADADDR(ram_code));
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} GROUP_DATA_LINK_IN(RAM_ILM, ROMABLE_REGION)
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}
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