31 lines
740 B
C
31 lines
740 B
C
/*
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* Copyright (c) 2021 Tokita, Hiroshi <tokita.hiroshi@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file SoC configuration macros for the GigaDevice GD32VF103 processor
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*/
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#ifndef RISCV_GD32VF103_SOC_H_
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#define RISCV_GD32VF103_SOC_H_
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#include <soc_common.h>
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#include <zephyr/devicetree.h>
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/* Timer configuration */
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#define RISCV_MTIME_BASE DT_REG_ADDR_BY_IDX(DT_NODELABEL(mtimer), 0)
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#define RISCV_MTIMECMP_BASE DT_REG_ADDR_BY_IDX(DT_NODELABEL(mtimer), 1)
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#ifndef _ASMLANGUAGE
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#include <zephyr/toolchain.h>
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#include <gd32vf103.h>
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/* The GigaDevice HAL headers define this, but it conflicts with the Zephyr can.h */
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#undef CAN_MODE_NORMAL
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#endif /* !_ASMLANGUAGE */
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#endif /* RISCV_GD32VF103_SOC_H */
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