99 lines
3.1 KiB
C
99 lines
3.1 KiB
C
/*
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* Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _MEC172X_VBAT_H
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#define _MEC172X_VBAT_H
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#include <stdint.h>
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#include <stddef.h>
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/* VBAT Registers Registers */
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#define MCHP_VBAT_MEMORY_SIZE 128u
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/* Offset 0x00 Power-Fail and Reset Status */
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#define MCHP_VBATR_PFRS_OFS 0u
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#define MCHP_VBATR_PFRS_MASK 0x7cu
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#define MCHP_VBATR_PFRS_SYS_RST_POS 2u
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#define MCHP_VBATR_PFRS_JTAG_POS 3u
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#define MCHP_VBATR_PFRS_RESETI_POS 4u
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#define MCHP_VBATR_PFRS_WDT_POS 5u
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#define MCHP_VBATR_PFRS_SYSRESETREQ_POS 6u
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#define MCHP_VBATR_PFRS_VBAT_RST_POS 7u
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#define MCHP_VBATR_PFRS_SYS_RST BIT(2)
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#define MCHP_VBATR_PFRS_JTAG BIT(3)
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#define MCHP_VBATR_PFRS_RESETI BIT(4)
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#define MCHP_VBATR_PFRS_WDT BIT(5)
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#define MCHP_VBATR_PFRS_SYSRESETREQ BIT(6)
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#define MCHP_VBATR_PFRS_VBAT_RST BIT(7)
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/* Offset 0x08 32K Clock Source register */
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#define MCHP_VBATR_CS_OFS 0x08u
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#define MCHP_VBATR_CS_MASK 0x71f1u
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#define MCHP_VBATR_CS_SO_EN_POS 0
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#define MCHP_VBATR_CS_XTAL_EN_POS 8
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#define MCHP_VBATR_CS_XTAL_SEL_POS 9
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#define MCHP_VBATR_CS_XTAL_DHC_POS 10
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#define MCHP_VBATR_CS_XTAL_CNTR_POS 11
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#define MCHP_VBATR_CS_PCS_POS 16
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#define MCHP_VBATR_CS_DI32_VTR_OFF_POS 18
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/* Enable and start internal 32KHz Silicon Oscillator */
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#define MCHP_VBATR_CS_SO_EN BIT(0)
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/* Enable and start the external crystal */
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#define MCHP_VBATR_CS_XTAL_EN BIT(8)
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/* single ended crystal on XTAL2 instead of parallel across XTAL1 and XTAL2 */
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#define MCHP_VBATR_CS_XTAL_SE BIT(9)
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/* disable XTAL high startup current */
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#define MCHP_VBATR_CS_XTAL_DHC BIT(10)
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/* crystal amplifier gain control */
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#define MCHP_VBATR_CS_XTAL_CNTR_MSK 0x1800u
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#define MCHP_VBATR_CS_XTAL_CNTR_DG 0x0800u
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#define MCHP_VBATR_CS_XTAL_CNTR_RG 0x1000u
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#define MCHP_VBATR_CS_XTAL_CNTR_MG 0x1800u
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/* Select source of peripheral 32KHz clock */
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#define MCHP_VBATR_CS_PCS_MSK 0x30000u
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/* 32K silicon OSC when chip powered by VBAT or VTR */
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#define MCHP_VBATR_CS_PCS_VTR_VBAT_SO 0u
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/* 32K external crystal when chip powered by VBAT or VTR */
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#define MCHP_VBATR_CS_PCS_VTR_VBAT_XTAL 0x10000u
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/* 32K input pin on VTR. Switch to Silicon OSC on VBAT */
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#define MCHP_VBATR_CS_PCS_VTR_PIN_SO 0x20000u
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/* 32K input pin on VTR. Switch to crystal on VBAT */
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#define MCHP_VBATR_CS_PCS_VTR_PIN_XTAL 0x30000u
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/* Disable internal 32K VBAT clock source when VTR is off */
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#define MCHP_VBATR_CS_DI32_VTR_OFF BIT(18)
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/*
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* Monotonic Counter least significant word (32-bit), read-only.
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* Increments by one on read.
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*/
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#define MCHP_VBATR_MCNT_LSW_OFS 0x20u
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/* Monotonic Counter most significant word (32-bit). Read-Write */
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#define MCHP_VBATR_MCNT_MSW_OFS 0x24u
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/* ROM Feature register */
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#define MCHP_VBATR_ROM_FEAT_OFS 0x28u
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/* Embedded Reset Debounce Enable register */
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#define MCHP_VBATR_EMBRD_EN_OFS 0x34u
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#define MCHP_VBATR_EMBRD_EN BIT(0)
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/** @brief VBAT Register Bank (VBATR) */
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struct vbatr_regs {
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volatile uint32_t PFRS;
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uint32_t RSVD1[1];
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volatile uint32_t CLK32_SRC;
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uint32_t RSVD2[5];
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volatile uint32_t MCNT_LO;
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volatile uint32_t MCNT_HI;
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uint32_t RSVD3[3];
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volatile uint32_t EMBRD_EN;
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};
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#endif /* #ifndef _MEC172X_VBAT_H */
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