190 lines
5.0 KiB
C
190 lines
5.0 KiB
C
/*
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* Copyright (c) 2019 Microchip Technology Inc.
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* Copyright (c) 2016 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr.h>
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#include <sys/sys_io.h>
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#include <sys/__assert.h>
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#include <pm/pm.h>
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#include <soc.h>
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#include <arch/cpu.h>
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#include <arch/arm/aarch32/cortex_m/cmsis.h>
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#ifndef CONFIG_PM_DEVICE
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#include "device_power.h"
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#endif
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#include "soc_power_debug.h"
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#define HTMR_0_XEC_REG_BASE \
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((struct htmr_regs *)(DT_REG_ADDR(DT_NODELABEL(hibtimer0))))
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#define PCR_XEC_REG_BASE \
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((struct pcr_regs *)(DT_REG_ADDR(DT_NODELABEL(pcr))))
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/*
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* Deep Sleep
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* Pros:
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* Lower power dissipation, 48MHz PLL is off
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* Cons:
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* Longer wake latency. CPU start running on ring oscillator
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* between 16 to 25 MHz. Minimum 3ms until PLL reaches lock
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* frequency of 48MHz.
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*
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* Implementation Notes:
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* We touch the Cortex-M's primary mask and base priority registers
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* because we do not want to enter an ISR immediately upon wake.
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* We must restore any hardware state that was modified upon sleep
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* entry before allowing interrupts to be serviced. Zephyr arch level
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* does not provide API's to manipulate both primary mask and base priority.
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*
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* DEBUG NOTES:
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* If a JTAG/SWD debug probe is connected driving TRST# high and
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* possibly polling the DUT then MEC1501 will not shut off its 48MHz
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* PLL. Firmware should not disable JTAG/SWD in the EC subsystem
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* while a probe is using the interface. This can leave the JTAG/SWD
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* TAP controller in a state of requesting clocks preventing the PLL
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* from being shut off.
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*/
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/* NOTE: Zephyr masks interrupts using BASEPRI before calling PM subsystem */
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static void z_power_soc_deep_sleep(void)
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{
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struct pcr_regs *pcr = PCR_XEC_REG_BASE;
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struct htmr_regs *htmr0 = HTMR_0_XEC_REG_BASE;
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uint32_t basepri = 0U;
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uint32_t temp = 0U;
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PM_DP_ENTER();
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__disable_irq();
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basepri = __get_BASEPRI();
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#ifndef CONFIG_PM_DEVICE
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soc_deep_sleep_periph_save();
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soc_deep_sleep_wake_en();
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soc_deep_sleep_non_wake_en();
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#endif
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/*
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* Enable deep sleep mode in CM4 and MEC172x.
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* Enable CM4 deep sleep and sleep signals assertion on WFI.
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* Set MCHP Heavy sleep (PLL OFF when all CLK_REQ clear) and SLEEP_ALL
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* to assert SLP_EN to all peripherals on WFI.
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* Set PRIMASK = 1 so on wake the CPU will not vector to any ISR.
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* Set BASEPRI = 0 to allow any priority to wake.
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*/
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SCB->SCR |= BIT(2);
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pcr->SYS_SLP_CTRL = MCHP_PCR_SYS_SLP_HEAVY;
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pcr->OSC_ID = pcr->SYS_SLP_CTRL;
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#ifdef DEBUG_DEEP_SLEEP_CLK_REQ
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soc_debug_sleep_clk_req();
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#endif
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__set_BASEPRI(0);
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__WFI(); /* triggers sleep hardware */
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__NOP();
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__NOP();
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/*
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* Clear SLEEP_ALL manually since we are not vectoring to an ISR until
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* PM post ops. This de-asserts peripheral SLP_EN signals.
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*/
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pcr->SYS_SLP_CTRL = 0U;
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SCB->SCR &= ~BIT(2);
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/* Wait for PLL to lock with timeout */
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htmr0->PRLD = 0U; /* make sure its stopped */
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htmr0->CTRL = 0U; /* 30.5 us per tick */
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htmr0->PRLD = 216U; /* ~6.6 ms 2x the expected lock time */
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temp = htmr0->PRLD;
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while ((pcr->OSC_ID & MCHP_PCR_OSC_ID_PLL_LOCK) == 0) {
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temp = htmr0->PRLD;
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if (!temp) {
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break;
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}
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}
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htmr0->PRLD = 0U; /* stop */
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__set_BASEPRI(basepri);
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#ifndef CONFIG_PM_DEVICE
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soc_deep_sleep_non_wake_dis();
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soc_deep_sleep_wake_dis();
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soc_deep_sleep_periph_restore();
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#endif
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PM_DP_EXIT();
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}
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/*
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* Light Sleep
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* Pros:
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* Fast wake response:
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* Cons:
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* Higher power dissipation, 48MHz PLL remains on.
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*
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* When the kernel calls this it has masked interrupt by setting NVIC BASEPRI
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* equal to a value equal to the highest Zephyr ISR priority. Only NVIC
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* exceptions will be served.
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*/
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static void z_power_soc_sleep(void)
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{
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struct pcr_regs *pcr = PCR_XEC_REG_BASE;
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__disable_irq();
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SCB->SCR &= ~BIT(2);
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pcr->SYS_SLP_CTRL = MCHP_PCR_SYS_SLP_LIGHT;
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pcr->OSC_ID = pcr->SYS_SLP_CTRL;
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__set_BASEPRI(0);
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__WFI(); /* triggers sleep hardware */
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__NOP();
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__NOP();
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pcr->SYS_SLP_CTRL = 0U;
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}
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/*
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* Called from pm_system_suspend(int32_t ticks) in subsys/power.c
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* For deep sleep pm_system_suspend has executed all the driver
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* power management call backs.
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*/
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__weak void pm_state_set(enum pm_state state, uint8_t substate_id)
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{
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ARG_UNUSED(substate_id);
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switch (state) {
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case PM_STATE_SUSPEND_TO_IDLE:
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z_power_soc_sleep();
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break;
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case PM_STATE_SUSPEND_TO_RAM:
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z_power_soc_deep_sleep();
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break;
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default:
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break;
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}
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}
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/*
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* Zephyr PM code expects us to enabled interrupt at post op exit. Zephyr used
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* arch_irq_lock() which sets BASEPRI to a non-zero value masking all interrupts
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* preventing wake. MCHP z_power_soc_(deep)_sleep sets PRIMASK=1 and BASEPRI=0
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* allowing wake from any enabled interrupt and prevent CPU from entering any
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* ISR on wake except for faults. We re-enable interrupt by setting PRIMASK to 0.
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* Side-effect is we set BASEPRI=0. Is this the same value as Zephyr uses during
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* NVIC initialization?
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*/
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__weak void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
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{
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switch (state) {
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case PM_STATE_SUSPEND_TO_IDLE:
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case PM_STATE_SUSPEND_TO_RAM:
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__enable_irq();
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break;
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default:
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irq_unlock(0); /* this writes CM4 BASEPRI=0 */
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break;
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}
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}
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