385 lines
9.5 KiB
C
385 lines
9.5 KiB
C
/*
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* Copyright (c) 2019 Microchip Technology Inc.
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* Copyright (c) 2016 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr.h>
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#include <sys/sys_io.h>
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#include <sys/__assert.h>
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#include <pm/pm.h>
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#include <soc.h>
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#include "device_power.h"
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#define ADC_0_XEC_REG_BASE \
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((struct adc_regs *)(DT_REG_ADDR(DT_NODELABEL(adc0))))
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#define ECIA_XEC_REG_BASE \
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((struct ecia_named_regs *)(DT_REG_ADDR(DT_NODELABEL(ecia))))
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#define ECS_XEC_REG_BASE \
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((struct ecs_regs *)(DT_REG_ADDR(DT_NODELABEL(ecs))))
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#define PECI_XEC_REG_BASE \
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((struct peci_regs *)(DT_REG_ADDR(DT_NODELABEL(pcr))))
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#define PCR_XEC_REG_BASE \
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((struct pcr_regs *)(DT_REG_ADDR(DT_NODELABEL(pcr))))
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#define TFDP_0_XEC_REG_BASE \
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((struct tfdp_regs *)(DT_REG_ADDR(DT_NODELABEL(tfdp0))))
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#define UART_0_XEC_REG_BASE \
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((struct uart_regs *)(DT_REG_ADDR(DT_NODELABEL(uart0))))
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#define UART_1_XEC_REG_BASE \
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((struct uart_regs *)(DT_REG_ADDR(DT_NODELABEL(uart1))))
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#define VBATR_XEC_REG_BASE \
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((struct vbatr_regs *)(DT_REG_ADDR_BY_NAME(DT_NODELABEL(pcr), vbatr)))
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#define VBATM_XEC_BASE_ADDR \
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((uintptr_t)(DT_REG_ADDR(DT_NODELABEL(bbram))))
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#define BTMR16_0_ADDR DT_REG_ADDR(DT_NODELABEL(timer0))
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#define BTMR16_1_ADDR DT_REG_ADDR(DT_NODELABEL(timer1))
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#define BTMR16_2_ADDR DT_REG_ADDR(DT_NODELABEL(timer2))
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#define BTMR16_3_ADDR DT_REG_ADDR(DT_NODELABEL(timer3))
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#define BTMR32_0_ADDR DT_REG_ADDR(DT_NODELABEL(timer4))
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#define BTMR32_1_ADDR DT_REG_ADDR(DT_NODELABEL(timer5))
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#define VBATM_XEC_ADDR DT_REG_ADDR(DT_NODELABEL(vbr))
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#ifdef DEBUG_DEEP_SLEEP_CLK_REQ
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void soc_debug_sleep_clk_req(void)
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{
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struct ecs_regs *ecs = ECS_XEC_REG_BASE;
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struct pcr_regs *pcr = PCR_XEC_REG_BASE;
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uintptr_t vbm_addr = VBATM_XEC_BASE_ADDR;
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/* Save status to debug LPM been blocked */
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for (int i = 0; i < 5; i++) {
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sys_write32(pcr->CLK_REQ[i], vbm_addr);
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vbm_addr += 4;
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}
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sys_write32(pcr->SYS_SLP_CTRL, vbm_addr);
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vbm_addr += 4;
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sys_write32(ecs->SLP_STS_MIRROR, vbm_addr);
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}
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#endif
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/*
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* Allow peripherals connected to external masters to wake the PLL but not
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* the EC. Once the peripheral has serviced the external master the PLL
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* will be turned back off. For example, if the eSPI master requests eSPI
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* configuration information or state of virtual wires the EC doesn't need
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* to be involved. The hardware can power on the PLL long enough to service
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* the request and then turn the PLL back off. The SMBus and I2C peripherals
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* in slave mode can also make use of this feature.
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*/
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void soc_deep_sleep_non_wake_en(void)
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{
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#ifdef CONFIG_ESPI
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struct ecia_named_regs *regs = ECIA_XEC_REG_BASE;
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regs->GIRQ22.SRC = UINT32_MAX;
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regs->GIRQ22.EN_SET = MCHP_ESPI_WK_CLK_GIRQ_BIT;
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#endif
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}
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void soc_deep_sleep_non_wake_dis(void)
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{
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#ifdef CONFIG_ESPI
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struct ecia_named_regs *regs = ECIA_XEC_REG_BASE;
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regs->GIRQ22.EN_CLR = UINT32_MAX;
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regs->GIRQ22.SRC = UINT32_MAX;
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#endif
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}
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/* When MEC172x drivers are power-aware this should be move there */
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void soc_deep_sleep_wake_en(void)
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{
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#if defined(CONFIG_KSCAN) || DT_NODE_HAS_STATUS(DT_NODELABEL(ps2_0), okay)
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struct ecia_named_regs *regs = ECIA_XEC_REG_BASE;
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#if defined(CONFIG_KSCAN)
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/* Enable PLL wake via KSCAN */
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regs->GIRQ21.SRC = MCHP_KEYSCAN_GIRQ_BIT;
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regs->GIRQ21.EN_SET = MCHP_KEYSCAN_GIRQ_BIT;
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(ps2_0), okay)
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/* Enable PS2_0B_WK */
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regs->GIRQ21.SRC = MCHP_PS2_0_PORT0B_WK_GIRQ_BIT;
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regs->GIRQ21.EN_SET = MCHP_PS2_0_PORT0B_WK_GIRQ_BIT;
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#endif
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#endif
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}
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void soc_deep_sleep_wake_dis(void)
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{
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(ps2_0), okay)
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struct ecia_named_regs *regs = ECIA_XEC_REG_BASE;
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/* Enable PS2_0B_WK */
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regs->GIRQ21.EN_CLR = MCHP_PS2_0_PORT0B_WK_GIRQ_BIT;
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regs->GIRQ21.SRC = MCHP_PS2_0_PORT0B_WK_GIRQ_BIT;
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#endif
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}
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/* Variables used to save various HW state */
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#ifdef DEEP_SLEEP_PERIPH_SAVE_RESTORE
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const struct ds_timer_info ds_timer_tbl[NUM_DS_TIMER_ENTRIES] = {
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{
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(uintptr_t)(BTMR16_0_ADDR + MCHP_BTMR_CTRL_OFS),
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MCHP_BTMR_CTRL_HALT, 0
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},
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{
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(uintptr_t)(BTMR16_1_ADDR + MCHP_BTMR_CTRL_OFS),
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MCHP_BTMR_CTRL_HALT, 0
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},
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{
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(uintptr_t)(BTMR16_2_ADDR + MCHP_BTMR_CTRL_OFS),
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MCHP_BTMR_CTRL_HALT, 0
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},
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{
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(uintptr_t)(BTMR16_3_ADDR + MCHP_BTMR_CTRL_OFS),
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MCHP_BTMR_CTRL_HALT, 0
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},
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{
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(uintptr_t)(BTMR32_0_ADDR + MCHP_BTMR_CTRL_OFS),
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MCHP_BTMR_CTRL_HALT, 0
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},
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{
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(uintptr_t)(BTMR32_1_ADDR + MCHP_BTMR_CTRL_OFS),
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MCHP_BTMR_CTRL_HALT, 0
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},
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};
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static struct ds_dev_info ds_ctx;
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static void deep_sleep_save_ecs(void)
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{
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struct ecs_regs *regs = ECS_XEC_REG_BASE;
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ds_ctx.ecs[0] = regs->ETM_CTRL;
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ds_ctx.ecs[1] = regs->DEBUG_CTRL;
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#ifdef DEEP_SLEEP_JTAG
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regs->ETM_CTRL = 0;
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regs->DEBUG_CTRL = 0x00;
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#endif
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}
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#ifdef DEEP_SLEEP_UART_SAVE_RESTORE
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static void deep_sleep_save_uarts(void)
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{
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struct uart_regs *regs = UART_0_XEC_REG_BASE;
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ds_ctx.uart_info[0] = regs->ACTV;
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if (ds_ctx.uart_info[0]) {
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while ((regs->LSR & MCHP_UART_LSR_TEMT) == 0) {
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}
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}
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regs->ACTV = 0;
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regs = UART_1_XEC_REG_BASE;
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ds_ctx.uart_info[1] = regs->ACTV;
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if (ds_ctx.uart_info[1]) {
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while ((regs->LSR & MCHP_UART_LSR_TEMT) == 0) {
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}
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}
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regs->ACTV = 0;
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}
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#endif
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static void deep_sleep_save_timers(void)
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{
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const struct ds_timer_info *p;
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uint32_t i;
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p = &ds_timer_tbl[0];
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for (i = 0; i < NUM_DS_TIMER_ENTRIES; i++) {
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ds_ctx.timers[i] = sys_read32(p->addr);
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if (p->stop_mask) {
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sys_write32(ds_ctx.timers[i] | p->stop_mask, p->addr);
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} else {
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sys_write32(0, p->addr);
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}
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p++;
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}
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}
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static void deep_sleep_restore_ecs(void)
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{
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#ifdef DEEP_SLEEP_JTAG
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struct ecs_regs *regs = ECS_XEC_REG_BASE;
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regs->ETM_CTRL = ds_ctx.ecs[0];
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regs->DEBUG_CTRL = ds_ctx.ecs[1];
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#endif
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}
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#ifdef DEEP_SLEEP_UART_SAVE_RESTORE
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static void deep_sleep_restore_uarts(void)
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{
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struct uart_regs *regs0 = UART_0_XEC_REG_BASE;
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struct uart_regs *regs1 = UART_1_XEC_REG_BASE;
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regs0->ACTV = ds_ctx.uart_info[0];
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regs1->ACTV = ds_ctx.uart_info[1];
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}
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#endif
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static void deep_sleep_restore_timers(void)
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{
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const struct ds_timer_info *p;
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uint32_t i, temp;
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p = &ds_timer_tbl[0];
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for (i = 0; i < NUM_DS_TIMER_ENTRIES; i++) {
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if (p->stop_mask) {
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temp = sys_read32(p->addr) & ~(p->stop_mask);
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sys_write32(temp, p->addr);
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} else {
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sys_write32(ds_ctx.timers[i] & ~p->restore_mask,
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p->addr);
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}
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p++;
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}
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}
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#ifdef DEEP_SLEEP_PERIPH_SAVE_RESTORE_EXTENDED
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static void deep_sleep_save_blocks(void)
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{
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struct tfdp_regs *tfdp = TFDP_0_XEC_REG_BASE;
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struct ecs_regs *ecs = ECS_XEC_REG_BASE;
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#ifdef CONFIG_ADC
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struct adc_regs *adc0 = ADC_0_XEC_REG_BASE;
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/* ADC deactivate */
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adc0->CONTROL &= ~(MCHP_ADC_CTRL_ACTV);
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#endif
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#ifdef CONFIG_PECI
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struct peci_regs *peci = PECI_XEC_REG_BASE;
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ds_ctx.peci_info.peci_ctrl = peci->CONTROL;
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ds_ctx.peci_info.peci_dis = ecs->PECI_DIS;
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ecs->PECI_DIS |= MCHP_ECS_PECI_DISABLE;
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#endif
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#ifdef CONFIG_I2C
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for (size_t n = 0; n > MCHP_I2C_SMB_INSTANCES; n++) {
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uint32_t addr = MCHP_I2C_SMB_BASE_ADDR(n) +
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MCHP_I2C_SMB_CFG_OFS;
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uint32_t regval = sys_read32(addr);
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ds_ctx.smb_info[n] = regval;
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sys_write32(regval & ~(MCHP_I2C_SMB_CFG_ENAB), addr);
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}
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#endif
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/* Disable comparator if enabled */
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if (ecs->CMP_CTRL & BIT(0)) {
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ds_ctx.comp_en = 1;
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ecs->CMP_CTRL &= ~(MCHP_ECS_ACC_EN0);
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}
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#if defined(CONFIG_TACH_XEC) || defined(CONFIG_PWM_XEC)
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struct pcr_regs *pcr = PCR_XEC_REG_BASE;
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/* This low-speed clock derived from the 48MHz clock domain is used as
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* a time base for PWMs and TACHs
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* Set SLOW_CLOCK_DIVIDE = CLKOFF to save additional power
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*/
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ds_ctx.slwclk_info = pcr->SLOW_CLK_CTRL;
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pcr->SLOW_CLK_CTRL &= (~MCHP_PCR_SLOW_CLK_CTRL_100KHZ &
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MCHP_PCR_SLOW_CLK_CTRL_MASK);
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#endif
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/* TFDP HW block is not expose to any Zephyr subsystem */
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if (tfdp->CTRL & MCHP_TFDP_CTRL_EN) {
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ds_ctx.tfdp_en = 1;
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tfdp->CTRL &= ~MCHP_TFDP_CTRL_EN;
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}
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/* Port 80 TODO Do we need to do anything? MEC172x BDP does not
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* include a timer so it should de-assert its CLK_REQ in response
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* to SLP_EN 0->1.
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*/
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}
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static void deep_sleep_restore_blocks(void)
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{
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struct tfdp_regs *tfdp = TFDP_0_XEC_REG_BASE;
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struct ecs_regs *ecs = ECS_XEC_REG_BASE;
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#ifdef CONFIG_ADC
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struct adc_regs *adc0 = ADC_0_XEC_REG_BASE;
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adc0->CONTROL |= MCHP_ADC_CTRL_ACTV;
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#endif
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#ifdef CONFIG_PECI
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struct peci_regs *peci = PECI_XEC_REG_BASE;
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ecs->PECI_DIS = ds_ctx.peci_info.peci_dis;
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peci->CONTROL = ds_ctx.peci_info.peci_ctrl;
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#endif
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#ifdef CONFIG_I2C
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for (size_t n = 0; n > MCHP_I2C_SMB_INSTANCES; n++) {
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uint32_t addr = MCHP_I2C_SMB_BASE_ADDR(n) +
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MCHP_I2C_SMB_CFG_OFS;
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sys_write32(ds_ctx.smb_info[n], addr);
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}
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#endif
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/* Restore comparator control values */
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if (ds_ctx.comp_en) {
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ecs->CMP_CTRL |= MCHP_ECS_ACC_EN0;
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}
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#if defined(CONFIG_TACH_XEC) || defined(CONFIG_PWM_XEC)
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struct pcr_regs *pcr = PCR_XEC_REG_BASE;
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/* Restore slow clock control */
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pcr->SLOW_CLK_CTRL = ds_ctx.slwclk_info;
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#endif
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/* TFDP HW block is not expose to any Zephyr subsystem */
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if (ds_ctx.tfdp_en) {
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tfdp->CTRL |= MCHP_TFDP_CTRL_EN;
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}
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}
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#endif /* DEEP_SLEEP_PERIPH_SAVE_RESTORE_EXTENDED */
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void soc_deep_sleep_periph_save(void)
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{
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#ifdef DEEP_SLEEP_PERIPH_SAVE_RESTORE_EXTENDED
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deep_sleep_save_blocks();
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#endif
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deep_sleep_save_ecs();
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deep_sleep_save_timers();
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#ifdef DEEP_SLEEP_UART_SAVE_RESTORE
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deep_sleep_save_uarts();
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#endif
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}
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void soc_deep_sleep_periph_restore(void)
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{
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deep_sleep_restore_ecs();
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#ifdef DEEP_SLEEP_UART_SAVE_RESTORE
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deep_sleep_restore_uarts();
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#endif
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deep_sleep_restore_timers();
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#ifdef DEEP_SLEEP_PERIPH_SAVE_RESTORE_EXTENDED
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deep_sleep_restore_blocks();
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#endif
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}
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#else
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void soc_deep_sleep_periph_save(void)
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{
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}
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void soc_deep_sleep_periph_restore(void)
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{
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}
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#endif /* DEEP_SLEEP_PERIPH_SAVE_RESTORE */
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