40 lines
584 B
Plaintext
40 lines
584 B
Plaintext
/*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Copyright (C) 2021, Intel Corporation
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*
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*/
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/dts-v1/;
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#include <intel/intel_socfpga_agilex.dtsi>
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/ {
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model = "Intel SoC FPGA Agilex";
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compatible = "intel,socfpga-agilex";
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#address-cells = <1>;
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#size-cells = <1>;
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chosen {
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zephyr,console = &uart0;
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zephyr,shell-uart = &uart0;
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zephyr,sram = &mem0;
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};
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};
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&uart0 {
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status = "okay";
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current-speed = <115200>;
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};
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&qspi {
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status = "okay";
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mt25qu02g@0 {
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compatible = "micron,mt25qu02g";
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reg = <0>;
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size = <DT_SIZE_M(256*8)>; /* in bits */
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status = "okay";
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};
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};
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