181 lines
3.6 KiB
Plaintext
181 lines
3.6 KiB
Plaintext
/*
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* Copyright (c) 2018-2021 Linaro Limited
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* Copyright 2022 Arm Limited and/or its affiliates <open-source-office@arm.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <arm/armv8.1-m.dtsi>
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#include <zephyr/dt-bindings/i2c/i2c.h>
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#include <zephyr/dt-bindings/input/input-event-codes.h>
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#include <mem.h>
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/ {
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compatible = "arm,mps3-an547";
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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led0 = &led_0;
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led1 = &led_1;
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sw0 = &user_button_0;
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sw1 = &user_button_1;
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};
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chosen {
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zephyr,console = &uart0;
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zephyr,shell-uart = &uart0;
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zephyr,sram = &dtcm;
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zephyr,flash = &itcm;
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};
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leds {
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compatible = "gpio-leds";
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led_0: led_0 {
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gpios = <&gpio_led0 0>;
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label = "USERLED0";
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};
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led_1: led_1 {
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gpios = <&gpio_led0 1>;
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label = "USERLED1";
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};
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led_2: led_2 {
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gpios = <&gpio_led0 2>;
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label = "USERLED2";
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};
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led_3: led_3 {
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gpios = <&gpio_led0 3>;
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label = "USERLED3";
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};
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led_4: led_4 {
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gpios = <&gpio_led0 4>;
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label = "USERLED4";
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};
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led_5: led_5 {
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gpios = <&gpio_led0 5>;
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label = "USERLED5";
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};
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led_6: led_6 {
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gpios = <&gpio_led0 6>;
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label = "USERLED6";
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};
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led_7: led_7 {
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gpios = <&gpio_led0 7>;
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label = "USERLED7";
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};
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led_8: led_8 {
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gpios = <&gpio_led0 8>;
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label = "PB1LED";
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};
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led_9: led_9 {
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gpios = <&gpio_led0 9>;
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label = "PB2LED";
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};
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};
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gpio_keys {
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compatible = "gpio-keys";
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user_button_0: button_0 {
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label = "USERPB0";
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gpios = <&gpio_button 0>;
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zephyr,code = <INPUT_KEY_0>;
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};
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user_button_1: button_1 {
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label = "USERPB1";
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gpios = <&gpio_button 1>;
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zephyr,code = <INPUT_KEY_1>;
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};
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};
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ethosu {
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#address-cells = <1>;
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#size-cells = <0>;
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interrupt-parent = <&nvic>;
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ethosu0: ethosu@48102000 {
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compatible = "arm,ethos-u";
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reg = <0x48102000>;
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interrupts = <56 3>;
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secure-enable;
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privilege-enable;
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status = "okay";
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m55";
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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mpu: mpu@e000ed90 {
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compatible = "arm,armv8.1m-mpu";
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reg = <0xe000ed90 0x40>;
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};
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};
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};
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/* We utilize the secure addresses, if you subtract 0x10000000
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* you'll get the non-secure alias
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*/
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itcm: itcm@10000000 { /* alias @ 0x0 */
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compatible = "zephyr,memory-region";
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reg = <0x10000000 DT_SIZE_K(512)>;
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zephyr,memory-region = "ITCM";
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};
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sram: sram@11000000 { /* alias @ 0x01000000 */
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compatible = "zephyr,memory-region", "mmio-sram";
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reg = <0x11000000 DT_SIZE_M(2)>;
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zephyr,memory-region = "SRAM";
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};
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dtcm: dtcm@30000000 { /* alias @ 0x20000000 */
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compatible = "zephyr,memory-region";
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reg = <0x30000000 DT_SIZE_K(512)>;
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zephyr,memory-region = "DTCM";
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};
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isram: sram@31000000 {/* alias @ 0x21000000 */
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compatible = "zephyr,memory-region", "mmio-sram";
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reg = <0x31000000 DT_SIZE_M(4)>;
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zephyr,memory-region = "ISRAM";
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};
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/* DDR4 - 2G, alternates non-secure/secure every 256M */
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ddr4: memory@60000000 {
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device_type = "memory";
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compatible = "zephyr,memory-region";
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reg = <0x60000000 DT_SIZE_M(256)
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0x70000000 DT_SIZE_M(256)
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0x80000000 DT_SIZE_M(256)
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0x90000000 DT_SIZE_M(256)
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0xa0000000 DT_SIZE_M(256)
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0xb0000000 DT_SIZE_M(256)
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0xc0000000 DT_SIZE_M(256)
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0xd0000000 DT_SIZE_M(256)>;
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zephyr,memory-region = "DDR4";
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};
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soc {
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peripheral@50000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x50000000 0x10000000>;
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#include "mps3_an547-common.dtsi"
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <3>;
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};
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