155 lines
3.8 KiB
C
155 lines
3.8 KiB
C
/*
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* Copyright (c) 2016 Piotr Mienkowski
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* Copyright (c) 2019-2023 Gerson Fernando Budke <nandojve@gmail.com>
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* SPDX-License-Identifier: Apache-2.0
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*/
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/** @file
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* @brief Atmel SAM V71 MCU initialization code
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*
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* This file provides routines to initialize and support board-level hardware
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* for the Atmel SAM V71 MCU.
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*/
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#include <zephyr/kernel.h>
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#include <zephyr/device.h>
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#include <zephyr/init.h>
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#include <zephyr/cache.h>
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#include <zephyr/arch/cache.h>
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#include <soc.h>
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#include <cmsis_core.h>
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#include <zephyr/logging/log.h>
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#define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
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LOG_MODULE_REGISTER(soc);
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/**
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* @brief Setup various clocks on SoC at boot time.
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*
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* Setup Slow, Main, PLLA, Processor and Master clocks during the device boot.
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* It is assumed that the relevant registers are at their reset value.
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*/
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static ALWAYS_INLINE void clock_init(void)
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{
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/* Switch the main clock to the internal OSC with 12MHz */
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soc_pmc_switch_mainck_to_fastrc(SOC_PMC_FAST_RC_FREQ_12MHZ);
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/* Switch MCK (Master Clock) to the main clock */
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soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_MAIN_CLK);
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EFC->EEFC_FMR = EEFC_FMR_FWS(0) | EEFC_FMR_CLOE;
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soc_pmc_enable_clock_failure_detector();
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if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_SLCK)) {
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soc_supc_slow_clock_select_crystal_osc();
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}
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if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_MAINCK)) {
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/*
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* Setup main external crystal oscillator.
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*/
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/* We select maximum setup time.
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* While start up time could be shortened
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* this optimization is not deemed
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* critical now.
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*/
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soc_pmc_switch_mainck_to_xtal(false, 0xff);
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}
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/*
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* Set FWS (Flash Wait State) value before increasing Master Clock
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* (MCK) frequency.
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* TODO: set FWS based on the actual MCK frequency and VDDIO value
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* rather than maximum supported 150 MHz at standard VDDIO=2.7V
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*/
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EFC->EEFC_FMR = EEFC_FMR_FWS(5) | EEFC_FMR_CLOE;
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/*
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* Setup PLLA
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*/
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/*
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* PLL clock = Main * (MULA + 1) / DIVA
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*
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* By default, MULA == 24, DIVA == 1.
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* With main crystal running at 12 MHz,
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* PLL = 12 * (24 + 1) / 1 = 300 MHz
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*
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* With Processor Clock prescaler at 1
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* Processor Clock (HCLK)=300 MHz.
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*/
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soc_pmc_enable_pllack(CONFIG_SOC_ATMEL_SAM_PLLA_MULA, 0x3Fu,
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CONFIG_SOC_ATMEL_SAM_PLLA_DIVA);
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soc_pmc_enable_upllck(0x3Fu);
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/*
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* Final setup of the Master Clock
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*/
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/* Setting PLLA as MCK, first prescaler, then divider and source last */
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soc_pmc_mck_set_prescaler(1);
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soc_pmc_mck_set_divider(CONFIG_SOC_ATMEL_SAM_MDIV);
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soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_PLLA_CLK);
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/* Disable internal fast RC if we have an external crystal oscillator */
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if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_MAINCK)) {
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soc_pmc_osc_disable_fastrc();
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}
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}
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void z_arm_platform_init(void)
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{
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if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_WAIT_MODE)) {
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/*
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* Instruct CPU to enter Wait mode instead of Sleep mode to
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* keep Processor Clock (HCLK) and thus be able to debug
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* CPU using JTAG.
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*/
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soc_pmc_enable_waitmode();
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}
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/*
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* DTCM is enabled by default at reset, therefore we have to disable
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* it first to get the caches into a state where then the
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* sys_cache*-functions can enable them, if requested by the
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* configuration.
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*/
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SCB_InvalidateDCache();
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SCB_DisableDCache();
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/*
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* Enable the caches only if configured to do so.
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*/
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sys_cache_instr_enable();
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sys_cache_data_enable();
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/* Setup system clocks */
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clock_init();
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}
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/**
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* @brief Perform basic hardware initialization at boot.
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*
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* This needs to be run at the very beginning.
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* So the init priority has to be 0 (zero).
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*
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* @return 0
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*/
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static int atmel_samv71_init(void)
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{
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/* Check that the CHIP CIDR matches the HAL one */
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if (CHIPID->CHIPID_CIDR != CHIP_CIDR) {
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LOG_WRN("CIDR mismatch: chip = 0x%08x vs HAL = 0x%08x",
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(uint32_t)CHIPID->CHIPID_CIDR, (uint32_t)CHIP_CIDR);
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}
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return 0;
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}
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SYS_INIT(atmel_samv71_init, PRE_KERNEL_1, 0);
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