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The Ambiq MSPI controller is implemented using the MSPI bus API. The hardware supports up to 48MHz octal SDR with XIP, scrambling and hardware command queue features. Signed-off-by: Swift Tian <swift.tian@ambiq.com> |
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.. | ||
CMakeLists.txt | ||
Kconfig | ||
Kconfig.ambiq | ||
Kconfig.mspi_emul | ||
mspi_ambiq.h | ||
mspi_ambiq_ap3.c | ||
mspi_emul.c |