294 lines
9.0 KiB
C
294 lines
9.0 KiB
C
/*
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* Copyright (c) 2015 Intel Corporation.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/**
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* @file pinmux operations for Quark_D2000
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*/
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#include <nanokernel.h>
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#include <device.h>
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#include <init.h>
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#include <pinmux.h>
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#include <sys_io.h>
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#include "pinmux/pinmux.h"
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#ifndef CONFIG_PINMUX_DEV
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#define PRINT(...) { ; }
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#else
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#if defined(CONFIG_PRINTK)
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#include <misc/printk.h>
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#define PRINT printk
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#elif defined(CONFIG_STDOUT_CONSOLE)
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#define PRINT printf
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#endif /* CONFIG_PRINTK */
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#endif /*CONFIG_PINMUX_DEV */
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#define MASK_2_BITS 0x3
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const uint32_t PINMUX_PULLUP_OFFSET = 0x00;
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const uint32_t PINMUX_SLEW_OFFSET = 0x10;
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const uint32_t PINMUX_INPUT_OFFSET = 0x20;
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const uint32_t PINMUX_SELECT_OFFSET = 0x30;
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#define PINMUX_SELECT_REGISTER(base, reg_offset) \
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(base + PINMUX_SELECT_OFFSET + (reg_offset << 2))
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/*
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* A little decyphering of what is going on here:
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*
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* Each pinmux register rperesents a bank of 16 pins, 2 bits per pin for a total
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* of four possible settings per pin.
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*
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* The first argument to the macro is name of the uint32_t's that is being used
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* to contain the bit patterns for all the configuration registers. The pin
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* number divided by 16 selects the correct register bank based on the pin
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* number.
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*
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* The pin number % 16 * 2 selects the position within the register bank for the
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* bits controlling the pin.
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*
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* All but the lower two bits of the config values are masked off to ensure
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* that we don't inadvertently affect other pins in the register bank.
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*/
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#define PIN_CONFIG(A, _pin, _func) \
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(A[((_pin) / 16)] |= ((0x3 & (_func)) << (((_pin) % 16) * 2)))
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#define PINMUX_MAX_REGISTERS 2
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/***************************
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* PINMUX mapping
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*
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* The following lines detail the possible options for the pinmux and their
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* associated pins and ball points.
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* This is the full pinmap that we have available on the board for configuration
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* including the ball position and the various modes that can be set. In the
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* _pinmux_defaults we do not spend any time setting values that are using mode
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* A as the hardware brings up all devices by default in mode A.
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*/
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/* pin, ball, mode A, mode B, mode C */
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/* 0 F00, gpio_0, ai_0, spi_m_ss0 */
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/* 1 F01, gpio_1, ai_1, spi_m_ss1 */
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/* 2 F02, gpio_2, ai_2, spi_m_ss2 */
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/* 3 F03, gpio_3, ai_3, spi_m_ss3 */
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/* 4 F04, gpio_4, ai_4, rtc_clk_out */
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/* 5 F05, gpio_5, ai_5, sys_clk_out */
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/* 6 F06, gpio_6, ai_6, i2c_scl */
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/* 7 F07, gpio_7, ai_7, i2c_sda */
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/* 8 F08, gpio_8, ai_8, spi_s_sclk */
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/* 9 F09, gpio_9, ai_9, spi_s_sdin */
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/* 10 F10, gpio_10, ai_10, spi_s_sdout */
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/* 11 F11, gpio_11, ai_11, spi_s_scs */
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/* 12 F12, gpio_12, ai_12, uart_a_txd */
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/* 13 F13, gpio_13, ai_13, uart_a_rxd */
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/* 14 F14, gpio_14, ai_14, uart_a_rts */
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/* 15 F15, gpio_15, ai_15, uart_a_cts */
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/* 16 F16, gpio_16, ai_16, spi_m_sclk */
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/* 17 F17, gpio_17, ai_17, spi_m_mosi */
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/* 18 F18, gpio_18, ai_18, spi_m_miso */
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/* 19 F19, tdo, gpio_19, pwm0 */
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/* 20 F20, trst_n, gpio_20, uart_b_txd */
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/* 21 F21, tck, gpio_21, uart_b_rxd */
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/* 22 F22, tms, gpio_22, uart_b_rts */
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/* 23 F23, tdi, gpio_23, uart_b_cts */
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/* 24 F24, gpio_24, lpd_sig_out, pwm1 */
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/******** End PINMUX mapping **************************/
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static void _pinmux_defaults(uint32_t base)
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{
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uint32_t mux_config[PINMUX_MAX_REGISTERS] = { 0, 0 };
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int i = 0;
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PIN_CONFIG(mux_config, 0, PINMUX_FUNC_C);
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PIN_CONFIG(mux_config, 3, PINMUX_FUNC_B);
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PIN_CONFIG(mux_config, 4, PINMUX_FUNC_B);
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PIN_CONFIG(mux_config, 6, PINMUX_FUNC_C);
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PIN_CONFIG(mux_config, 7, PINMUX_FUNC_C);
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PIN_CONFIG(mux_config, 12, PINMUX_FUNC_C);
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PIN_CONFIG(mux_config, 13, PINMUX_FUNC_C);
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PIN_CONFIG(mux_config, 14, PINMUX_FUNC_C);
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PIN_CONFIG(mux_config, 15, PINMUX_FUNC_C);
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PIN_CONFIG(mux_config, 16, PINMUX_FUNC_C);
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PIN_CONFIG(mux_config, 17, PINMUX_FUNC_C);
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PIN_CONFIG(mux_config, 18, PINMUX_FUNC_C);
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for (i = 0; i < PINMUX_MAX_REGISTERS; i++) {
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PRINT("PINMUX: configuring register i=%d reg=%x", i,
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mux_config[i]);
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sys_write32(mux_config[i], PINMUX_SELECT_REGISTER(base, i));
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}
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}
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static void _quark_d2000_set_mux(uint32_t base, uint32_t pin, uint8_t func)
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{
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/*
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* The register is a single 32-bit value, with CONFIG_PINMUX_NUM_PINS
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* bits set in it. Each bit represents the input enable status of the
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* pin.
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*/
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uint32_t enable_mask = (func & 0x01) << pin;
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uint32_t pin_mask = 0x1 << pin;
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volatile uint32_t *mux_register = (uint32_t *)(base);
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(*(mux_register)) = (((*(mux_register)) & ~pin_mask) | enable_mask);
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}
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#ifdef CONFIG_PINMUX_DEV
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static int pinmux_dev_set(struct device *dev, uint32_t pin, uint32_t func)
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{
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struct pinmux_config * const pmux = dev->config->config_info;
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/*
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* the registers are 32-bit wide, but each pin requires 2 bits
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* to set the mode (A, B, C, or D). As such we only get 16
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* pins per register... this can be accomplished by right shifting by 4.
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* Only in this case we are using it for a byte offset, so we are only
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* going to shift by 2 (avoids the multiplication).
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*/
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uint32_t register_offset = (pin >> 4);
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/*
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* Now figure out what is the full address for the register
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* we are looking for. Add the base register to the register_mask
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*/
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volatile uint32_t *mux_register =
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(uint32_t *)PINMUX_SELECT_REGISTER(pmux->base_address, register_offset);
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/*
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* Finally grab the pin offset within the register
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*/
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uint32_t pin_no = pin % 16;
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/*
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* The 2-bits is for the mode of each pin. The value 2 repesents the
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* bits needed for each pin's mode in the PMUX_SEL register.
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*/
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uint32_t pin_mask = MASK_2_BITS << (pin_no << 1);
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uint32_t mode_mask = func << (pin_no << 1);
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(*(mux_register)) = ((*(mux_register)) & ~pin_mask) | mode_mask;
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return DEV_OK;
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}
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static int pinmux_dev_get(struct device *dev, uint32_t pin, uint32_t *func)
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{
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struct pinmux_config * const pmux = dev->config->config_info;
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/*
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* the registers are 32-bit wide, but each pin requires 2 bits
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* to set the mode (A, B, C, or D). As such we only get 16
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* pins per register... hence the math for the register mask.
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*/
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uint32_t register_offset = pin >> 4;
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/*
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* Now figure out what is the full address for the register
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* we are looking for. Add the base register to the register_mask
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*/
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volatile uint32_t *mux_register =
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(uint32_t *)PINMUX_SELECT_REGISTER(pmux->base_address, register_offset);
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/*
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* Finally grab the pin offset within the register
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*/
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uint32_t pin_no = pin % 16;
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/*
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* The value 3 is used because that is 2-bits for the mode of each
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* pin. The value 2 repesents the bits needed for each pin's mode.
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*/
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uint32_t pin_mask = MASK_2_BITS << (pin_no << 1);
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uint32_t mode_mask = (*(mux_register)) & pin_mask;
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uint32_t mode = mode_mask >> (pin_no << 1);
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*func = mode;
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return DEV_OK;
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}
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#else
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static int pinmux_dev_set(struct device *dev, uint32_t pin, uint32_t func)
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{
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ARG_UNUSED(dev);
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ARG_UNUSED(pin);
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ARG_UNUSED(func);
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PRINT("ERROR: %s is not enabled", __func__);
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return DEV_NOT_CONFIG;
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}
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static int pinmux_dev_get(struct device *dev, uint32_t pin, uint32_t *func)
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{
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ARG_UNUSED(dev);
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ARG_UNUSED(pin);
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ARG_UNUSED(func);
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PRINT("ERROR: %s is not enabled", __func__);
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return DEV_NOT_CONFIG;
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}
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#endif /* CONFIG_PINMUX_DEV */
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static int pinmux_pullup_set(struct device *dev, uint32_t pin,
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uint8_t func)
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{
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struct pinmux_config * const pmux = dev->config->config_info;
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_quark_d2000_set_mux(pmux->base_address + PINMUX_PULLUP_OFFSET, pin,
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func);
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return DEV_OK;
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}
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static int pinmux_input_enable(struct device *dev, uint32_t pin,
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uint8_t func)
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{
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struct pinmux_config * const pmux = dev->config->config_info;
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_quark_d2000_set_mux(pmux->base_address + PINMUX_INPUT_OFFSET, pin,
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func);
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return DEV_OK;
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}
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static struct pinmux_driver_api api_funcs = {
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.set = pinmux_dev_set,
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.get = pinmux_dev_get,
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.pullup = pinmux_pullup_set,
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.input = pinmux_input_enable
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};
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int pinmux_initialize(struct device *port)
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{
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struct pinmux_config *pmux = port->config->config_info;
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port->driver_api = &api_funcs;
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_pinmux_defaults(pmux->base_address);
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/* Enable the UART RX pin to receive input */
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_quark_d2000_set_mux(pmux->base_address + PINMUX_INPUT_OFFSET, 5, 0x1);
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return DEV_OK;
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}
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struct pinmux_config board_pmux = {
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.base_address = CONFIG_PINMUX_BASE,
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};
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DEVICE_INIT(pmux, PINMUX_NAME, &pinmux_initialize,
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NULL, &board_pmux,
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SECONDARY, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
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