108 lines
3.3 KiB
C
108 lines
3.3 KiB
C
/*
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* Copyright (c) 2019, NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <init.h>
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#include <fsl_iomuxc.h>
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#include <fsl_gpio.h>
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static int mimxrt1010_evk_init(const struct device *dev)
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{
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ARG_UNUSED(dev);
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CLOCK_EnableClock(kCLOCK_Iomuxc);
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CLOCK_EnableClock(kCLOCK_IomuxcSnvs);
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio1), okay)
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IOMUXC_SetPinMux(IOMUXC_GPIO_11_GPIOMUX_IO11, 0);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_11_GPIOMUX_IO11,
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_PUE(1) |
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IOMUXC_SW_PAD_CTL_PAD_PUS(2) |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(4));
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IOMUXC_GPR->GPR26 &= ~(IOMUXC_GPR_GPR26_GPIO_SEL(1 << 11));
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio2), okay)
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IOMUXC_SetPinMux(IOMUXC_GPIO_SD_05_GPIO2_IO05, 0);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_05_GPIO2_IO05,
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_PUE(1) |
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IOMUXC_SW_PAD_CTL_PAD_PUS(2) |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(4));
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#endif
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/* MCUX SDK sets the drive strength of pins on RT1010 to 4 by default,
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* hence the difference between the drive strength selected here and in other
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* board pinmux files
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*/
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpuart1), okay) && CONFIG_SERIAL
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/* LPUART1 TX/RX */
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IOMUXC_SetPinMux(IOMUXC_GPIO_09_LPUART1_RXD, 0);
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IOMUXC_SetPinMux(IOMUXC_GPIO_10_LPUART1_TXD, 0);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_09_LPUART1_RXD,
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(4));
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IOMUXC_SetPinConfig(IOMUXC_GPIO_10_LPUART1_TXD,
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(4));
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpi2c1), okay) && CONFIG_I2C
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/* LPI2C1 SCL, SDA */
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IOMUXC_SetPinMux(IOMUXC_GPIO_01_LPI2C1_SDA, 1);
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IOMUXC_SetPinMux(IOMUXC_GPIO_02_LPI2C1_SCL, 1);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_02_LPI2C1_SCL,
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IOMUXC_SW_PAD_CTL_PAD_PUS(3) |
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_ODE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(4));
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IOMUXC_SetPinConfig(IOMUXC_GPIO_01_LPI2C1_SDA,
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IOMUXC_SW_PAD_CTL_PAD_PUS(3) |
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_ODE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(4));
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpspi1), okay) && CONFIG_SPI
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/* LPSPI1 CS, SDO, SDI, CLK exposed as pins 6, 8, 10, and 12 on J57 */
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IOMUXC_SetPinMux(IOMUXC_GPIO_AD_03_LPSPI1_SDI, 0U);
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IOMUXC_SetPinMux(IOMUXC_GPIO_AD_04_LPSPI1_SDO, 0U);
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IOMUXC_SetPinMux(IOMUXC_GPIO_AD_05_LPSPI1_PCS0, 0U);
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IOMUXC_SetPinMux(IOMUXC_GPIO_AD_06_LPSPI1_SCK, 0U);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_03_LPSPI1_SDI,
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(4));
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IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_04_LPSPI1_SDO,
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(4));
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IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_05_LPSPI1_PCS0,
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(4));
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IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_06_LPSPI1_SCK,
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IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
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IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
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IOMUXC_SW_PAD_CTL_PAD_DSE(4));
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#endif
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return 0;
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}
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SYS_INIT(mimxrt1010_evk_init, PRE_KERNEL_1, 0);
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